由於現今在積體電路系統中已經廣泛的應用系統晶片設計概念，且市場對於高效能系統單晶片的需求日漸增長，為了整合更多功能，時脈合成或是倍頻基本已經成為晶片內部中不可或缺的功能之一。且至今電路系統中的時脈訊號也愈來愈快，在晶片內部的非理想效應會使相位產生誤差以及延遲，這可能會嚴重影響整個系統的效能，因此數位系統電路整合的同步性也變得相當重要。隨時傳統常見的頻率合成器時常使用鎖相迴路（Phase-Locked Loop，PLL）設計，不過延遲鎖定迴路（Delay-Locked Loop，DLL）本身的時脈抖動(Jitter)以及穩定度方面表現相比於鎖相迴路(PLL)要好。一般而言，鎖相迴路(PLL)系統中含一電壓控制振盪器(Voltage Controlled Oscillator)，而此電路常會無法避免的抖動雜訊累積(Jitter accumulation)，而延遲鎖定迴路(DLL)中的電壓控制延遲線(Voltage-Controlled Delay Line，VCDL)不會將輸入的雜訊累積在其中，進而使得鎖相迴路(PLL)之雜訊抗擾性低於延遲鎖定迴路(DLL)。且延遲鎖定迴路(DLL)之迴路濾波器僅需要一階的電容，不同於鎖相迴路(PLL)需要二階以上的複雜濾波器來使系統穩定，如若設計不當可能會導致系統不穩定甚至失鎖。所以延遲鎖定迴路(DLL)此方面不僅降低了晶片面積，其系統容易穩定，也具有容易設計的特性。延遲鎖定迴路(DLL)已被廣泛地運用在許多需要時脈操作的電路上，如同步動態記憶體(SDRAM) 、數位信號處理器(DSP)、類比數位轉換器(ADC)等等，都可以使用延遲鎖定迴路來提供一個穩定的系統時脈，使電路可以達到預期的性能。

我們在架構中包含相位偵測器(Phase Detector，PD)、充電幫浦(Charge Pump，CP)、迴路濾波器(Loop Filter，LF)以及電壓控制延遲線(VCDL)，而為了提高延遲時間的解析度，運用了相位內插的方式。在系統鎖定後，系統後方相位內插電路(Interpolator)在電壓控制延遲線(VCDL)的延遲級中不同的相位之間做內插，來產生不同的相位，再經過控制選擇及相位比較來合成出不同的脈衝寬度的輸出，令此延遲鎖定迴路(DLL)可運用在脈衝寬度調變(PWM)，提高實用性。我們所提出的延遲鎖定迴路(DLL)架構採用台積電0.18-μm CMOS製程來實現，在工作電壓是1.8-V下，操作頻率為100-MHz，最小解析度為11.25˚，整體功耗為2.07 mW。

Due to the frequent use of the current chip, process technology is also more advanced, the clock signals in circuit system has been faster, and non-ideal effects within the chip will produce phase error and delay. This problem can seriously affect the overall system performance. Therefore, the clock synchronization of the digital system circuit becomes more important, especially in high-speed computing systems, the clock skew will be an important factor to determine the performance of the system. Clock synchronization technology usually through the phase-locked loop (PLL) and delay-locked loop (DLL) to eliminate the clock offset, increase the circuit stability, can produce a stable output oscillation frequency, and reduce product costs to increase product competitiveness. The jitter and stability of DLL is better than PLL. In general, a Voltage Controlled Oscillator (VCO) is included in a phase-locked loop (PLL) system, which is often unavoidable for Jitter accumulation, and Voltage-Controlled Delay Line (VCDL) in the Delay Lock Loop (DLL) doesn’t accumulate input noise, making the noise immunity of the phase-locked loop (PLL) lower than the delay-locked loop (DLL). And the delay-locked loop (DLL) circuit’s filter only requires a first-order capacitor, unlike the phase-locked loop (PLL) requires more than two-order complex filters to stabilize the system, if not properly designed may lead to system instability or even unlock. Therefore, the delay-locked loop (DLL) not only reduces the chip area, its system is easy to stabilize, but also has the characteristics of easy design.DLL has been widely used in the clock circuits, such as synchronous dynamic RAM (SDRAM), digital signal processor (DSP), analog-to-digital converter (ADC), etc., All of them can use the DLL to provide a stable system clock, so that the circuit can achieve the desired performance..

In this paper,we include phase detector (PD), Charge Pump(CP), Loop Filter (LF), and Voltage Control Delay Line (VCDL) in the architecture, and use phase interpolation to improve the resolution of delay. After the system is locked, the rear phase interpolator circuit (PI) interpolates between different phases in the delay stage of the voltage control delay line (VCDL) to produce different phases, and then synthesizes the output of different pulse widths by controlling selection and phase comparison, so that this delay-locked loop (DLL) can be used in pulse width modulation (PWM) to improve practicality. The proposed DLL architecture is based on 0.18μm 1P6M CMOS process with an operating voltage of 1.8 V, input reference frequency is 100 MHz, the minimum resolution is 11.25 degrees and the power consumption is 2.07 mW.

致謝	I
中文摘要	III
ABSTRACT	IV
目錄	VI
圖目錄	IX
表目錄	XII
第一章 序論	1
1.1 背景	1
1.2 論文架構	4
第二章 傳統延遲鎖定迴路架構原理與探討	5
2.1 傳統延遲鎖定迴路架構介紹	5
2.1.1 相位偵測器(PD)	6
2.1.2 充電幫浦(CP)與迴路濾波器(LF)	9
2.1.3 電壓控制延遲線(VCDL)	11
2.2 延遲鎖定迴路設計考量	13
2.2.1 鎖定範圍討論	13
2.2.2 系統穩定性分析	16
2.2.3 時脈抖動(Jitter)	20
第三章 相位內插電路系統設計	24
3.1 相位內插電路分析	24
3.1.1 數位式相位內插電路	27
3.1.2 類比式相位內插電路	28
3.2 數位類比混和式內插電路	30
第四章 具有相位對齊之高解析度脈衝寬度調變延遲鎖定迴路設計	33
4.1 具有內插電路之延遲鎖定迴路設計	33
4.1.1 內插電路應用於寬操作頻率範圍頻率產生器[18]	33
4.1.2 具有內插電路之延遲鎖定迴路	35
4.1.2.1 8 to 2相位選擇器(8 to 2 Phase select)	35
4.1.2.2 改良式相位內插電路(Modified Phase Interpolator)	36
4.2 具有相位對齊之高解析度脈衝寬度調變延遲鎖定迴路設計	39
4.2.1 延遲鎖定迴路(DLL)	39
4.2.1.1 動態相位偵測器(Phase Detector)	40
4.2.1.2 充電幫浦電路與迴路濾波器(Charge Pump & Loop Filter)	41
4.2.1.3 電壓控制延遲線(Voltage-Controlled Delay Line)	43
4.2.1.4 延遲鎖定迴路全系統模擬	45
4.3 具有脈衝寬度調變之延遲鎖定迴路	49
4.4 延遲鎖定迴路電路布局與模擬	52
4.5 文獻比較	53
4.6 電路佈局與量測考量	54
4.6.1 電路佈局	54
4.6.2 量測考量	55
第五章 結論與未來研究方向	57
參考文獻	58
 
圖目錄
圖 1.1系統時脈同步	1
圖 2.1傳統的延遲鎖定迴路方塊圖	5
圖 2.2相位偵測器(a)方塊圖 (b)特性圖	6
圖 2.3以XOR當相位偵測器(a)示意圖 (b)時序圖	7
圖 2.4死區(Dead zone)	7
圖 2.5三態相位偵測器(a)電路 (b)狀態圖	8
圖 2.6充電幫浦(a)示意圖 (b)時序圖	9
圖 2.7電壓控制延遲線架構圖	11
圖 2.8時間常數RC控制之延遲元件	12
圖 2.9可變電容之延遲元件	12
圖 2.10鎖定失敗(a)最小延遲狀態 (b)最大延遲狀態	14
圖 2.11諧波鎖定	15
圖 2.12傳統延遲鎖定迴路的線性模型	17
圖 2.13具輸入雜訊的延遲鎖定迴路(a)線性模型 (b)波德圖	19
圖 2.14具電源與基板雜訊的延遲鎖定迴路(a)線性模型 (b)波德圖	20
圖 2.15時脈抖動	21
圖 2.16雜訊累積(a)振盪器 (b)延遲線	21
圖 2.17週期抖動	22
圖 2.18週期循環對週期循環時脈抖動	23
圖 2.19長期時脈抖動	23
圖 3.1相位內插電路	24
圖 3.2相位內插 (a)電路模型 (b)時序圖	25
圖 3.3 (a)傳統數位方式實現的內插電路 (b)Short circuit現象	27
圖 3.4數位式可提供內插量調整之內插電路	28
圖 3.5類比式內插電路	29
圖 3.6共模回授系統之內插電路	29
圖 3.7雙向邊緣相位內插電路之模型圖	30
圖 3.8內插電路操作時序圖	31
圖 3.9混和式內插電路單元圖	32
圖 4.1寬操作頻率範圍相位內插電路架構圖	33
圖 4.2寬操作頻率範圍相位內插單元電路圖	34
圖 4.3具有內插電路之延遲鎖定迴路架構圖	35
圖 4.4 8 to 2相位選擇器示意圖	35
圖 4.5兩相位之相位內插電路架構	37
圖 4.6 延遲鎖定迴路之鎖定相位經內插系統輸出圖	37
圖 4.7延遲鎖定迴路之鎖定相位經內插系統輸出圖	38
圖 4.8 8 to 2相位選擇器示意圖	38
圖 4.9具有相位對齊之高解析度脈衝寬度調變延遲鎖定迴路架構圖	39
圖 4.10動態相位偵測器：(a)半穿透暫存器；(b)正緣觸發相位偵測器； (c)相位偵測器的操作時序圖	40
圖 4.11相位偵測器死區模擬圖	41
圖 4.12充電幫浦示意圖	42
圖 4.13充電幫浦電路架構圖	42
圖 4.14充電幫浦電流匹配圖	43
圖 4.15電壓控制延遲線電路架構圖	44
圖 4.16八相位之電壓控制延遲線輸出圖	44
圖 4.17各參數變異下電壓控制延遲線之KVCDL	45
圖 4.18延遲鎖定迴路追索狀態(TT 27)	45
圖 4.19延遲鎖定迴路鎖定狀態(TT 27)	46
圖 4.20回授時脈FOUT之眼圖	46
圖 4.21延遲鎖定迴路追索狀態(SS 0)	47
圖 4.22延遲鎖定迴路鎖定狀態(SS 0)	47
圖 4.23延遲鎖定迴路追索狀態(FF 75)	48
圖 4.24延遲鎖定迴路鎖定狀態(FF 75)	48
圖 4.25全系統經由內插電路得到之脈衝寬度調變輸出	49
圖 4.26經脈衝寬度調變後之輸出	50
圖 4.27相位內插後之結果誤差量	50
圖 4.28偏壓調整過後之內插結果誤差量	51
圖 4.29電路layout相對位置圖	54
圖 4.30各元件之電路佈局圖	54
圖 4.31量測環境及量測方式	55
圖 4.32環境對應之等效寄生效應	56
圖 4.33 LM317穩壓電路圖	56

 
表目錄
表 4.1 8 to 2相位選擇器真值表	36
表 4.2延遲鎖定迴路系統規格表	52
表 4.3延遲鎖定迴路各元件功率消耗	53
表 4.4文獻比較表	53

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