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系統識別號 U0002-3006201200484600
中文論文名稱 使用選擇器擴充方法達成高效率的測試壓縮架構
英文論文名稱 An Efficient Test Data Compression Scheme Using Selection Expansion
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 100
學期 2
出版年 101
研究生中文姓名 陳功瀚
研究生英文姓名 Kung-Han Chen
學號 699450085
學位類別 碩士
語文別 英文
口試日期 2012-06-13
論文頁數 48頁
口試委員 指導教授-饒建奇
委員-陳竹一
委員-梁新聰
中文關鍵字 積體電路  測試  自我測試 
英文關鍵字 VLSI  Testing  BIST 
學科別分類 學科別應用科學電機及電子
中文摘要 當現今的積體電路,功能越來越強大,相對地,邏輯閘數目也越來越多,也許是擁有兆級以上邏輯閘的電路。要測試這樣大的電路,變得越加困難,相當不容易。通常需要用到非常大量的測試資料才能完成測試。但是通常自動測試機台(Automatic Test Equipment,ATE)的記憶體容量並沒有這麼大,而且使用的測試資料數多時,將非常秏時及秏電。因此,必需將測試資料進行壓縮(test data compression)。我們利用多重輸入位移暫存器(MISR)可使一個進入的資料在硬體裡跑多次的特性,發展出我們的硬體架構。 本架構可使一個輸入資料在架構經過多個週期,進而產生大量資料。我們利用多重輸入位移暫存器作為我們解壓縮器的核心。並且利用高期消去法得到我們在測試機台的資料,或者說壓縮後的資料。在本架構中,我們利用一個選擇器和多個正反器(Flip-Flop)來擴充我們的資料,因為多重輸入位移暫存器裡的正反器會與多個選擇器相連,藉此擴充資料。在自動測試機台內的資料經由我們的解壓縮器反解後,得到了大量而有效的測試資料。而在選擇器產生資料後,我們會經由一組的正反器將其資料進行儲存。而我們可以讓這些正反器配合一些多工器,這樣一來我們只要在需要改變資料時才給予這多工器轉換的資料,如此一來,我們就不需要太頻繁的去改變資料,進而可以節省功率消秏。而一個自動測試機器的資料將在我們的架構中跑多次的特性,在這一時間中,硬體電路可以去作其他的事情,如此一來將可提升速度。
英文摘要 Because MISR (Multiple input shift register) can use one ATE data run a lot of times in it. We use this characteristic to let one data run lots of times in MISR to generate a lot of patterns. MISR is the foundation of our decompressor .And using Gauss-Elimination to get the ATE data. Selection with Flip-Flop can spread MISR data, because one Flip-Flop of MISR connected with two MUXs of Selection. The Selection connected with the MISR. Flip-Flops are connected with the Selection. The original ATE is spreading by our decompressor architecture. And using the Flip-Flops can restore the bits in it, we just changing the Flip-Flops bits when the data is changed. Because the bits of Flip-Flops are not changing frequently, we can save power. And one ATE data run a lot of cycles in the decompressor architecture, so the time is saving by this way.
論文目次 Table Of Content
中文摘要........................................................................................................................I
英文摘要.......................................................................................................................II
Table of Content ..........................................................................................................III
List of Figures ..............................................................................................................V
List of Tables ..............................................................................................................VII
Chapter 1. INTRODUCTION.................................................................................... 1
1-1 Motivation ....................................................................................................... 1
1-2 Issue Overview ................................................................................................ 1
1-3 Thesis Overview.............................................................................................. 3
Chapter 2. PAPER USES TESTING KNOWLEDGE................................................ 5
2-1 How to detect a fault........................................................................................ 5
2-2 Fault Simulation .............................................................................................. 7
2-3 Scan-Chain Design .......................................................................................... 8
2-4 Compression Ratio ........................................................................................ 11
2-5 Shift Power.................................................................................................... 11
2-6 Capture Power ............................................................................................... 13
2-7 Linear Feedback Shift Register (LFSR) ......................................................... 14
Chapter 3. PROPOSED HARDWARE ARCHITECTURE...................................... 16
3-1 Overview Of Architecture.............................................................................. 16
3-2 Detail Of Dcompressor Architecture .............................................................. 20
Chapter 4. PROPOSED COMPRESSING ALGORITHM....................................... 26
4-2 Part A - Slice the original patterns.................................................................. 27
4-3 Part B - Getting solving vector....................................................................... 28
4-4 Part C - Getting ATE data.............................................................................. 34
IV
Chapter 5. SIMULATION RESULTS ..................................................................... 42
Chapter 6. CONCLUTIONS.................................................................................... 45
References............................................................................................................... 47

LIST OF FIGURES
Figure 2.1 OR-fault detect...................................................................................... 6
Figure 2.2 AND-fault detect................................................................................... 6
Figure 2.3Fault Coverage(FC) ............................................................................... 7
Figure 2.4 Parallel Fault Simulation....................................................................... 8
Figure 2.5 not easy to get fault in sequential circuit.............................................. 9
Figure 2.6 (a) a muxed-D scan element (b) a sample of scan-chain ...................... 9
Figure 2.7 Common Scan-Chain Circuit ...............................................................11
Figure 2.8 Shift Power Program Example ............................................................ 12
Figure 2.9 Capture Power Program Example........................................................ 13
Figure 2.10 Linear Feedback Shift Register ,LFSR ........................................... 15
Figure 3.1 Overview of test environment.............................................................. 17
Figure 3.2 Decompresion schema. detail of decompressor consists the
MISR,Selection, and Flip-Flops Array..................................................................... 18
Figure 3.3 A sample of MISR linked to Selection. .................................................. 20
Figure 3.4 A sample of MISR linked to Selection Mux. .......................................... 22
Figure 3.5 Set the decompressor in mode 0.......................................................... 23
Figure 3.6 Set the decompressor in mode 1.......................................................... 24
Figure 3.7 Mode 1 uses mask. If the bit of mask is 1, we pass it. If the bit of mask is
0, we set the bit in 0. .......................................................................................... 25
Figure 4. 1 Procedure of getting ATE data. ............................................................ 27
Figure 4.3 A sample of slicing original patterns..................................................... 28
VI
Figure 4.4 Example of getting solving vector from Vector Set (a) Getting desired
Selection from Vector Set (b) Getting MUX of Selection from desired Selection (c)
Getting solving Selection from desired Selection (d) Getting solving vector from
solving Selection and MUX of Selection................................................................ 31
Figure 4. 5 Example of MISR data ......................................................................... 34
Figure 4.6 (a)MISR architecture (b)the data after MISR run 3 cycles (c)
simplification data of (b)...........................................................................................35
Figure 4.7 Our Architecture Example of getting ATE data (a) solving vector (b)
select specific bits (c) the equations of specific bits (d) the seed (e) substitute (d)
to (c) will get the matrix (f) solving by Gauss-Elimination and get the ATE data .... 40
Figure 4. 8 An example of mode 1, we insert these data in Figure 4.5(c) cycle1.. 40
VII
LIST OF TABLES
Table 5.1 Comparison Our Results with Other Method ......................................... 42
Table 5.2 Data volume comparison results by using MinTest and other test set .... 43
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