淡江大學覺生紀念圖書館 (TKU Library)
進階搜尋


下載電子全文限經由淡江IP使用) 
系統識別號 U0002-2906200911353000
中文論文名稱 針對快速掃描測試具有功率導向的X填入方法
英文論文名稱 X-Filling Methodology for Power-Aware At-Speed Scan Testing
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 97
學期 2
出版年 98
研究生中文姓名 陳宗塘
研究生英文姓名 Tsung-Tang Chen
電子信箱 josephchen229551@gmail.com
學號 696450328
學位類別 碩士
語文別 中文
第二語文別 英文
口試日期 2009-06-09
論文頁數 51頁
口試委員 指導教授-嚴雨田
共同指導教授-饒建奇
委員-李建模
委員-梁新聰
委員-饒建奇
中文關鍵字 X填入  快速掃描測試  低功率 
英文關鍵字 X-filling  At-Speed Scan Testing  Low Power 
學科別分類 學科別應用科學電機及電子
中文摘要 一個ATPG-based技術的設計針對的是在掃描測試期間降低移動功率和捕捉功率被提出來而不會有錯誤涵蓋率的衝突,這篇論文提出一個X填入的方法被稱作是 Adjacent Backtracing fill (AB-fill)。兩種技術在ATPG裡被探究,鄰填入和回朔填入法在 Adjacent Backtracing fill中被使用,這是可以結合在ATPG演算法中當提供第一個測試樣本到待測電路去的同時作降低捕捉功率。在快速掃描測試中經過我們的AB-fill,測試樣本將部分指定值或是全部指定值分配成有小部分的不確定值作為測試壓縮用,這樣出來的測試樣本是具有低功率的特性。實驗數據是針對 ISCAS’89電路且分別地秀出的是與之前所提出來的方法在捕捉功率上降的多。
英文摘要 ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents an X-filling approach called Adjacent Backtracing fill (AB-fill). Adjacent Backtracing fill, in which both the adjacent and backtracing filling algorithm are used, is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT. After our AB-fill approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of unknown value (x) bits as in test compression, and it is a low capture power and considering the shift power test pattern. Experimental results for ISCAS’89 benchmark circuits show that the proposed scheme respectively outperforms previous method in capture power.
論文目次 中文摘要.............................................. I
英文摘要.............................................. II
Table of Contents..................................... III
List of Figures....................................... V
List of Tables........................................ VI

CHAPTER 1 INTRODUCTION................................ 1
1.1 Motivation........................................ 1
1.2 The Challenges of Low Power Scan-Testing for X-filling ...............................................4
1.3 Low Power Testing Techniques...................... 6
1.3.1 DFT –based..................................... 6
1.3.2 ATPG –based.................................... 8

CHAPTER 2 BACKGROUND AND PRELIMINARIES................ 12
2.1 Full-Scan Architecture............................ 12
2.2 Launch off Capture (LOC) and Launch off Shift (LOS) 15
2.3 Related Earlier Works ............................ 16
2.4 Power Dissipation and Power Issues................ 18

CHAPTER 3 PORPOSED METHODS.............................23
3.1 Basic Idea........................................ 23
3.2 Logic Simulation Algorithm.........................25
3.3 Backtracing Algorithm............................. 26
3.4 X-filling Algorithm.............................. 29
3.4.1 The First Part (DType-filling)...................30
3.4.2 The Second Part (EType-filling)................. 32
3.4.3 The Third Part (PI- and PPI filling).............34

CHAPTER 4 EXPERIMENTAL RESULTS........................ 39

CHAPTER 5 CONCLUSIONS AND FUTURE WORK................. 46
5.1 Conclusions....................................... 46
5.2 Future Work....................................... 46

REFERENCES............................................ 48

Figure 1.1 Shift power and capture power during scan testing.................................................3
Figure 2.1 Difficulty of detecting stuck-at-faults in a sequential circuit.....................................12
Figure 2.2 (a)A muxed-D scan cell (b)A sample scan chain..................................................13
Figure 2.3 Conventional full-scan designed circuit...13
Figure 2.4 Timing diagram of LOC tests...............15
Figure 2.5 LOC transition test.......................17
Figure 2.6 Types of classification for PPI and PPO parts..................................................18
Figure 2.7 Dynamic power dissipation in a CMOS logic gate...................................................19
Figure 2.8 Illustration of manufacturing yield loss..22
Figure 2.9 Example of weighted transition count......22
Figure 3.1 The correlation of the scan-out data and scan-in data................................................24
Figure 3.2 Our PI Relaxation for combinational circuit................................................24
Figure 3.3 The LCP TPG Algorithm.....................25
Figure 3.4 The backtracing algorithm.................27
Figure 3.5 The structural diagram of s27.............28
Figure 3.6 AB-fill for LCP TPG Algorithm.............29
Figure 3.7 The X-filling methods for PPI and PPO parts..................................................30
Figure 3.8 The X-filling method of CType.............30
Figure 3.9 The third part of AB-fill.................31
Figure 3.10 The X-filling method of DType.............32
Figure 3.11 The first part of AB-fill.................33
Figure 3.12 The X-filling method of EType.............34
Figure 3.13 The second part of AB-fill................35
Figure 3.14 The basis of our PI Relaxation............36
Figure 3.15 Algorithm of X-filling....................38
Figure 4.1 Transitional FFs for methods on s1196, s5378 and s9234..............................................43
Figure 4.2 Transitional FFs for methods on s13207, s15850 and s35932......................................44
Figure 4.3 Transitional FFs for methods on s38417 and s38584.................................................45

Table 4.1 The distribution of original types.........39
Table 4.2 The rate of reduction for the previous methodologies (s1196, s5378, s9234 and s13207..........41
Table 4.3 The rate of reduction for the previous methodologies (s15850, s35932, s38417 and s38584)......43
參考文獻 [1] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,” in Proc. IEEE VLSI Test Symp. (VTS’93), Atlantic City, NJ, USA, Apr. 6-8, 1993, pp. 4-9.
[2] P. Girad, “Survey of Low-Power Testing of VLSI Circuits,” IEEE Design & Test of Computers, vol. 19, no. 3, May/June, 2002, pp. 82-92.
[3] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, San Francisco: Elsevier, 2006.
[4] K. J. Lee, T. C. Huang, and J. J. Chen, “Peak-power reduction for multiple-scan circuits during test application,” in Proc. IEEE Asian Test Symp. (ATS’00), Taipei, Taiwan, Dec. 4-6, 2000, pp.453-458.
[5] X. Wen, K. Miyase, T. Suzuki, Y. Yamato, S. Kajihara, L.-T. Wang, and K. Saluja, “A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation,” in Proc. IEEE Int’l International Conference on Computer Design (ICCD’06), San Jose, CA, USA, Oct. 1-4, 2006, pp. 251-258.
[6] S. Wang and S. K. Gupta, “DS-LFSR: A New BIST TPG for Low Heat Dissipation,” in Proc. IEEE Int’l Test Conf. (ITC’97), Washington, DC, USA, Nov. 1-6, 1997, pp. 848-857.
[7] P. Rosinger, B. M. Al-Hashimi, and N. Nicolici. “Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no.7, Jul. 2004. pp. 1142-1153.
[8] S. Gerstendorfer and H. J. Wunderlich, “Minimized Power Consumption for Scan-Based BIST,” in Proc. IEEE Int’l Test Conf. (ITC’99), Atlantic City, NJ, USA, Sept. 28-30, 1999, pp. 77-84.
[9] V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. M. Reddy, “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits during Test Application,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, Dec. 1998, pp. 1325-1333.
[10] W.-D. Tseng, “Scan Chain Ordering Technique for Switching Activity Reduction during Scan Test,” IEE Proceedings on Computers and Digital Techniques, vol. 152, no. 5, Sept. 2005, pp. 609-617.
[11] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and A. Virazel, “Design of Routing-Constrained Low Power Scan Chains,” in Proc. Design Automation and Test in Europe conference and exhibition, Paris, France, Feb 16-20, 2004, pp. 62-67.
[12] L. Whetsel, “Adapting Scan Architectures for Low Power Operation,” in Proc. IEEE Int’l Test Conf. (ITC’00), Atlantic City, NJ, USA, Oct. 3-5, 2000, pp. 863-872.
[13] J. Saxena, K. M. Butler, and L. Whetsel, “An Analysis of Power Reduction Techniques in Scan Testing,” in Proc. IEEE Int’l Test Conf. (ITC’01), Baltimore, MD, USA, Oct. 30-Nov. 1, 2001, pp. 670-677.
[14] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, “A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores,” in Proc. IEEE Asian Test Symp. (ATS’01), Kyoto, Japan, Nov 19-21, 2001, pp. 253-258.
[15] T.-C. Huang and K.-J. Lee, “A Token Scan Architecture for Low-Power Testing,” in Proc. IEEE Int’l Test Conf. (ITC’01), Baltimore, MD, USA, Oct. 30-Nov. 1, 2001, pp 661-669.
[16] N. Nicolici and B. M. Al-Hashimi, “Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits,” IEEE Trans. Computers, vol. 51, no. 6, Jun. 2002, pp. 721-734
[17] R. Sankaralingam and N. A. Touba, “Reducing test power during test using programmable scan chain disable,” in Proc. The First IEEE International Workshop on Electronic Design, Test and Applications. (DELTA’02), Christchurch, New Zealand, Jan. 29-31, 2002, pp.159-163.
[18] S. Gerstendorfer and H.-J. Wunderlich, “Minimized Power Consumption for Scan-Based BIST,” in Proc. IEEE Int’l Test Conf. (ITC’01), Atlantic City, NJ, USA Sept. 28-30, 1999, pp. 77-84.
[19] R. Sankaralingam and N. A. Touba, “Inserting Test Points to Control Peak Power During Scan Testing”, in Proc. IEEE Int’l Symp. Defect and Fault Tolerance in VLSI Systems. (DFT’02), Vancouver, Canada, Nov. 6-8, 2002, pp. 138-146.
[20] T.-C. Huang and K.-J. Lee, “Reduction of Power Consumption in Scan-Based Circuits during Test Application by an Input Control Technique,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, Jul. 2001, pp. 911-917.
[21] E. Alpaslan, Y. Huang, X. Lin, W.-T. Cheng, J. Dworak, “Reducing Scan Shift Power at RTL,” in Proc. IEEE VLSI Test Symp. (VTS’08), San Diego, CA, USA, Apr. 27-May. 1, 2008, pp. 139-146.
[22] X. Wen, S. Kajihara, K. Miyase, T. Suzuki, K. Saluja, L.-T. Wang, K. Abdel-Hafez, and K. Kinoshita, “A New ATPG Method for Efficient Capture Power Reduction during Scan Testing,” in Proc. IEEE VLSI Test Symp. (VTS’06), Berkeley, CA, USA, Apr, 2006, pp.58-63.
[23] S. Wang and S. K. Gupta, “ATPG for Heat Dissipation Minimization during Test Application,” IEEE Trans. Computers, vol. 47, no. 2, Feb. 1998, pp. 256-262.
[24] S. Wang and S. K. Gupta, “ATPG for Heat Dissipation Minimization for Scan Testing,” in Proc. ACM/IEEE Design Auto. Conf. (DAC’97), New York, NY, USA, 1997, pp. 614-619.
[25] S. Chakravarty and V. Dabholkar, “Minimizing Power Dissipation in Scan Circuits during Test Application,” in Proc. IEEE Asian Test Symp. (ATS’94), Nara, Japan, Nov 15-17, 1994, pp. 51-56.
[26] P. Girard, C. Landrault, S. Pravossoudovitch and D.Severac, “Reducing Power Consumption during Test Application by Test Vector Ordering,” in Proc. Int’l Circuits and Systems Symp. (ISCAS’98), vol. 2, Monterey, CA, USA, May. 31-Jun. 3, 1998, pp. 296-299.
[27] P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A Test Vector Ordering Technique for Switching Activity Reduction during Test Operation,” in Proc. Great Lakes Symp. on VLSI (GLS-VLSI’ 99), Ypsilanti, MI, USA, Mar. 4-6, 1999, pp. 24-27.
[28] W.-D. Tseng and L.-J. Lee, “Reduction of Power Dissipation during Scan Testing by Test Vector Ordering,” IEEE 8th Int’l Workshop on Microprocessor Test & Verification. (MTV’07), Austin, TX, USA, Dec. 4-6, 2007.
[29] R. Sankaralingam, R. R. Oruganti, and N. A. Touba. “Static Compaction Techniques to Control Scan Vector Power Dissipation,” in Proc. IEEE VLSI Test Symp. (VTS’00), Montreal, QC, Canada, Apr. 30-May. 4, 2000, pp. 35-40.
[30] R. Sankaralingam and N. A. Touba, "Controlling Peak Power during Scan Testing," in Proc. IEEE VLSI Test Symp. (VTS’02), Apr. 28-May. 2, 2002. pp.153-159.
[31] X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K. Saluja, and K. Kinoshita, “On Low-Capture-Power Test Generation for Scan Testing,” in Proc. IEEE VLSI Test Symp. (VTS’05), Palm Springs, CA, USA, May. 1-5, 2005, pp. 265-270.
[32] X. Wen, Y. Yamashita, S. Morishima, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, “Low-Capture-Power Test Generation for Scan-Based At-Speed Testing,” in Proc. IEEE Int’l Test Conf. (ITC’05), Austin, TX, USA, Nov 8-10, 2005. pp 1-10.
[33] N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H.-J. Wunderlich, “Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics,” in Proc. Design & Test of Integrated Systems in Nanoscale Technology. (DTIS’06), Tunis, Tunisia, Sept. 5-7, 2006, pp. 359-364.
[34] Chandra, A. and Kapur, R., “Bounded Adjacent Fill for Low Capture Power Scan Testing”, VLSI Test Conf., 2008, pp. 131 - 138.
[35] Remersaro, S., X. Lin, Z. Zhang, Reddy, S. M., Pomeranz, I. and Rajski, J., “Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs”, Intl. Test Conf., Oct. 2006, pp. 1 - 10.
[36] X. Wen, Miyase, K., Kajihara, S., Suzuki, T., Yamato, Y., Girard, P., Ohsumi, Y. and L. T. Wang, “A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing”, Intl. Test Conf., Oct. 2007, pp. 1 - 10.
[37] H. Furukawa, X. Wen, K. Miyase, Y. Yamato, S. Kajihara, P. Girard, L.-T. Wang, M. Tehranipoor, “CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing”, IEEE Asian Test Symposium (ATS), 2008, pp.397 - 402.
[38] Savir, J. and Patil, S., “Broad-Side Delay Test”, IEEE Trans. Computer-Aided Design, Vol. 13, No.8, Aug. 1994, pp. 1057 - 1064.
[39] Savir, J. and Patil, S., “Scan-Based Transition Test”, IEEE Trans. Computer-Aided Design, Vol. 12, No.8, Aug. 1993, pp. 1232 - 1241.
[40] C. Kim and S.-M. Kang, “A Low-Swing Clock Double-Edge Triggered Flip-Flop,” IEEE J. Solid-State Circuits, vol. 37, no. 5, May. 2002, pp.648-652.
[41] C.-Y. Wang and K. Roy, “Maximum Power Estimation for CMOS Circuits Using Deterministic and Statistical Approaches,” IEEE Transactions on VLSI Systems, vol. 6, no. 1, Mar. 1998, pp. 134-140.
[42] N. Nicolici and X. Wen, “Embedded Tutorial on Low Power Test,” in Proc. European Test Symp. (ETS' 07), Freiburg, Germany, May. 20-24, 2007, pp. 202-207.
[43] K. Miyase and S. Kajihara, “XID: Don’t Care Identification of Test Patterns for Combinational Circuit,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 2, Feb. 2004. pp.321-326.
[44] N. Jha and S. Gupta, Testing of digital systems, Cambridge University Press, 2003.
[45] H. K. Lee and D. S. Ha, “Atalanta: an Efficient ATPG for Combinational Circuits,” Technical Report, 93-12, Dep't of Electrical Eng., Virginia Polytechnic Institute and State University, Blacksburg, Virginia, 1993.
[46] H. K. Lee and D. S. Ha, “HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 9, Sept. 1996, pp. 1048–1058.
[47] J. Saxena, K. M. Butler, V. B. Jayaram, et.al., "A Case Study of IR-drop in Structured At-Speed Testing", Proc ITC 2003, pp. 1098- 1104.
論文使用權限
  • 同意紙本無償授權給館內讀者為學術之目的重製使用,於2009-07-02公開。
  • 同意授權瀏覽/列印電子全文服務,於2009-07-02起公開。


  • 若您有任何疑問,請與我們聯絡!
    圖書館: 請來電 (02)2621-5656 轉 2281 或 來信