一個ATPG-based技術的設計針對的是在掃描測試期間降低移動功率和捕捉功率被提出來而不會有錯誤涵蓋率的衝突，這篇論文提出一個X填入的方法被稱作是 Adjacent Backtracing fill (AB-fill)。兩種技術在ATPG裡被探究，鄰填入和回朔填入法在 Adjacent Backtracing fill中被使用，這是可以結合在ATPG演算法中當提供第一個測試樣本到待測電路去的同時作降低捕捉功率。在快速掃描測試中經過我們的AB-fill，測試樣本將部分指定值或是全部指定值分配成有小部分的不確定值作為測試壓縮用，這樣出來的測試樣本是具有低功率的特性。實驗數據是針對 ISCAS’89電路且分別地秀出的是與之前所提出來的方法在捕捉功率上降的多。

ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents an X-filling approach called Adjacent Backtracing fill (AB-fill). Adjacent Backtracing fill, in which both the adjacent and backtracing filling algorithm are used, is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT. After our AB-fill approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of unknown value (x) bits as in test compression, and it is a low capture power and considering the shift power test pattern. Experimental results for ISCAS’89 benchmark circuits show that the proposed scheme respectively outperforms previous method in capture power.

中文摘要..............................................	I
英文摘要..............................................	II
Table of Contents.....................................	III
List of Figures.......................................	V
List of Tables........................................	VI
	
CHAPTER 1 INTRODUCTION................................	1
1.1 Motivation........................................	1
1.2 The Challenges of Low Power Scan-Testing for X-filling ...............................................4
1.3 Low Power Testing Techniques......................	6
1.3.1 DFT –based.....................................	6
1.3.2 ATPG –based....................................	8
	
CHAPTER 2 BACKGROUND AND PRELIMINARIES................	12
2.1 Full-Scan Architecture............................	12
2.2 Launch off Capture (LOC) and Launch off Shift (LOS) 15
2.3 Related Earlier Works ............................	16
2.4 Power Dissipation and Power Issues................	18
	
CHAPTER 3 PORPOSED METHODS.............................23
3.1 Basic Idea........................................	23
3.2 Logic Simulation Algorithm.........................25
3.3 Backtracing Algorithm.............................	26
3.4 X-filling Algorithm..............................	29
3.4.1 The First Part (DType-filling)...................30
3.4.2 The Second Part (EType-filling).................	32
3.4.3 The Third Part (PI- and PPI filling).............34
	
CHAPTER 4 EXPERIMENTAL RESULTS........................	39
	
CHAPTER 5 CONCLUSIONS AND FUTURE WORK.................	46
5.1 Conclusions.......................................	46
5.2 Future Work.......................................	46
	
REFERENCES............................................	48

Figure 1.1   Shift power and capture power during scan testing.................................................3
Figure 2.1   Difficulty of detecting stuck-at-faults in a sequential circuit.....................................12
Figure 2.2   (a)A muxed-D scan cell (b)A sample scan chain..................................................13
Figure 2.3   Conventional full-scan designed circuit...13
Figure 2.4   Timing diagram of LOC tests...............15
Figure 2.5   LOC transition test.......................17
Figure 2.6   Types of classification for PPI and PPO parts..................................................18
Figure 2.7   Dynamic power dissipation in a CMOS logic gate...................................................19
Figure 2.8   Illustration of manufacturing yield loss..22
Figure 2.9   Example of weighted transition count......22
Figure 3.1   The correlation of the scan-out data and scan-in data................................................24
Figure 3.2   Our PI Relaxation for combinational circuit................................................24
Figure 3.3   The LCP TPG Algorithm.....................25
Figure 3.4   The backtracing algorithm.................27
Figure 3.5   The structural diagram of s27.............28
Figure 3.6   AB-fill for LCP TPG Algorithm.............29
Figure 3.7   The X-filling methods for PPI and PPO parts..................................................30
Figure 3.8   The X-filling method of CType.............30
Figure 3.9   The third part of AB-fill.................31
Figure 3.10  The X-filling method of DType.............32
Figure 3.11  The first part of AB-fill.................33
Figure 3.12  The X-filling method of EType.............34
Figure 3.13  The second part of AB-fill................35
Figure 3.14  The basis of our PI Relaxation............36
Figure 3.15  Algorithm of X-filling....................38
Figure 4.1   Transitional FFs for methods on s1196, s5378 and s9234..............................................43
Figure 4.2   Transitional FFs for methods on s13207, s15850 and s35932......................................44
Figure 4.3   Transitional FFs for methods on s38417 and s38584.................................................45

Table 4.1   The distribution of original types.........39
Table 4.2   The rate of reduction for the previous methodologies (s1196, s5378, s9234 and s13207..........41
Table 4.3   The rate of reduction for the previous methodologies (s15850, s35932, s38417 and s38584)......43

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