系統晶片的設計通常需要使用多重相位時脈，鎖相迴路(Phase-Locked Loop, PLL)可以提供一個良好的時脈同步處理機制。然而，PLL本身是高階的迴路且VCO的時脈抖動(jitter)累積特性，會使得高效能的PLL設計變的更加複雜。因此，在延遲鎖定迴路(Delay-Locked Loops, DLL)中，由於jitter不會累積於電壓控制延遲線(Voltage-Controlled Delay Line, VCDL)，且其本質上是個穩定的一階系統，因此，DLL在使用上日益廣泛。
    雖然VCDL不會有jitter累積的問題，但在整個DLL迴路之中，仍會有元件誤差及走線延遲所產生的jitter量。所以在本論文的第一個部份，我們提出了雙迴路延遲鎖定迴路架構來改善這個問題。整個電路我們使用0.35um CMOS technology來製作，其操作範圍可由250MHz~ 450MHz， 而模擬的cycle-to-cycle jitter在250MHz時為21ps。
另外，當DLL啟動之後，往往需要一段時間才能鎖定輸出，這在系統中局部電路改變頻率時，將會拖慢系統的穩定時間。所以我們提出了一個可程式化的控制電路提供一個適當的電壓給回授濾波器，以加速DLL鎖定的時間。此外，我們同時提出一個新式的倍頻器，它不僅具有較少的元件，且其輸出的頻率可大幅的提升。在此倍頻器之中，VCDL採用虛擬差動延遲元件(pseudo-differential delay cells)的差動輸出當作倍頻器的輸入，藉以得到近似50%的工作週期(duty cycle)時脈。這一個電路是利用0.18um 1P6M CMOS製程實現，由模擬結果得知，DLL可操作頻率的範圍為從200MHz到2GHz。鎖定時間最少僅需要6個週期，且在320MHz時模擬的cycle-to-cycle jitter為31ps，此時功率消耗為25mW。

The multiphase clocks are usually required in a system-on-chip design. The phase-locked loop (PLL) provides a well locking loop for the synchronization of clocks. However, the inherent high-order loop in the PLL and the jitter accumulation of the VCO make it difficult to design a high-performance PLL. Consequently, the delay-locked loop (DLL) is increasingly preferred rather than PLL due to no jitter accumulation in the voltage-controlled delay line (VCDL) and it is inherently a stable first-order system.
   Although the problem of jitter accumulation does not exist in the VCDL, there remains some jitter resulted by the device mismatch and loop delay in DLL loop. Thus, in the first section of this thesis, we propose a new dual-loop DLL to reduce the resulted jitter. The prototype circuit has been fabricated in 0.35μm 2P4M CMOS technology. The proposed DLL can operate with the input frequency from 250MHz to 450MHz. The simulated cycle-to-cycle jitter of the DLL is 21 ps at a 250MHz of input frequency.
   Furthermore, the DLL often needs a lot of time to lock the output frequency while a subsystem changes the reference frequency. Therefore, in the second part of this thesis, a programmable controller combined with a voltage reference circuit is proposed here to provide the loop filter a proper voltage to speed the locking of the DLL. Besides, we also present a new frequency multiplier, which not only processes less number of devices but also increases the output frequency of the DLL substantially. For such a frequency multiplier, we use the differential output of the VCDL, which adopts pseudo-differential delay cells, as its input to derive a clock with a roughly 50% of duty cycle. The circuit has been fabricated in 0.18μm 1P6M CMOS technology. From the simulation results, the proposed DLL-based frequency multiplier can operate Sin a wide range from 200MHz to 2GHz. Meanwhile, at the frequencies in such range, the minimum locking time of the DLL can be as less as six clock cycles. The simulated cycle-to-cycle jitter of the DLL is 31 ps at a frequency of 320MHz. The power consumption of the presented DLL is 25mW with a 1.8V supply voltage.

TABLE OF CONTENTS


中文摘要………………………………………………………………..	I
英文摘要...……………………………………………………………...	III
Table of Contents ………………………………………….....	V

List of Figures ……………………………………………......	VIII
List of Tables …………………………………………………	XI
	
Chapter 1 INTRODUCTION ………………………………	1
	
1.1 Motivation …………………………………………………………………..	1
1.2 Thesis Overview ……………………………………………………………	2
	
Chapter 2 THE FUNDAMENTALS OF DLLS ....................	4
	
2.1 Concepts of DLL ….………………………………………………………..	4
     2.1.1 Basic Analysis of the DLL ……………………………….…………….	6
     2.1.2 Stability Analysis of the DLL ……………………….....……………...	7
2.2 Phase Noise and Jitter……………………………………………..	9
     2.2.1 Clock Jitter ……………………………………………………...…......	10
     2.2.2 Types of Clock Jitter …………………………………………..………	11
     2.2.3 Cycle-to-Cycle Jitter ……………………………………………..……	11
     2.2.4 Period Jitter ……………………….…………………...………..……..	12
     2.2.5 Long-Term Jitter ……………………….………………………..…….	14
2.3 Design Consideration of the DLL ………………….……………..	15
     2.3.1 Lock Time …………………….....…………………..…………..……..	15
     2.3.2 Jitter Performance ………….…………..……..………………..……..	16
2.4 Design of Analog Delay-Locked Loop …..………………………..	18
    2.4.1 Phase Detector (PD) ……………………………….…………………...	19
    2.4.2 Charge Pump (CP) …………………………………………………….	20
    2.4.3 Voltage-Controlled Delay Line (VCDL) …...…………………………	22
2.5 Design of Digital Delay-Locked Loop …..………………………..	24
    2.5.1 Register-Controlled DLL ………………………….…………………...	25
    2.5.2 Counter-Controlled DLL ………………………………………...…….	26
    2.5.3 Successive Approximation Register-Controlled DLL ……..…………	27
	
Chapter 3 THE DUAL-FEEDBACK DLL ………………...	30
	
3.1 The Locking Condition in the Conventioal DLLs ..........………...	31
3.2 The Description of the Proposed DLL Architecture …………..	33
    3.2.1 Two PFDs with Distinct Dead Zones ……….…….…………...……..	33
    3.2.2 Circuit Description ………………………………..…………………...	34
3.3 Circuit Implementation …………………………………….……..	38
    3.3.1 Front-End Delay Cell …….…….……………………………………	38
    3.3.2 Startup-Controlled Circuit …………………………………..………...	39
    3.3.3 Phase Frequency Detector …….……………….….…………………...	40
    3.3.4 Charge Pump ………..………………………………….……………...	41
    3.3.5 Delay Cell …………………………………………..…………………...	42
3.4 Simulation Results ………………………………………………...	45
3.5 Experimental Results …………………….………………………..	48
3.6 Conclusions ………………………..…..…………………..……….	52
	
Chapter 4 THE FAST-LOCKING DLL …………………...	53
	
4.1 Introduction to the DLL-Based Frequency Multiplier ………..	53
4.2 Architecture and Description of the Proposed DLL …………….	56
    4.2.1 A Fast-Locking DLL ……………………………………………………	56
    4.2.2 The Swithcing Algorithm for the Control Voltage ……………………	58
    4.2.3 Frequency Multiplier……………………………………………………	60
4.3 Building Blocks Design ………………………...………….............	61
    4.3.1 Delay Cells ………………………………………………………………	61
    4.3.2 Programmable Charging Circuit (PCC) ...…………….………………	63
    4.3.3 Start-Controlled Circuit …………………………………......................	65
    4.3.4 Frequency Multiplier ..............................................……........................	66
4.4 Simulation Results …………………...………...………….............	68
4.5 Conclusions ………...…………………………...………….............	72
	
Chapter 5 CONCLUSIONS …………………………………	75
	
References …………………………………………………….	77



LIST OF FIGURES


Figure 2.1     Simplified block diagram of the conventional analog DLL………	4
Figure 2.2     The first type of DLL …………………….………………………	6
Figure 2.3    The second type of DLL ……………..…………………………...	6
Figure 2.4     Small signal AC mode of the conventional analog DLL ………...	7
Figure 2.5     Waveform timing variations …………………………………...…	10
Figure 2.6     Cycle-to-cycle jitter ………………………...…………………….	12
Figure 2.7     Period jitter ……………………………………………………….	12
Figure 2.8     Peak-to-peak jitter ………………..................................................	13
Figure 2.9     RMS jitter ………………………………………………………...	14
Figure 2.10    Long-term jitter …………………………..………………………	15
Figure 2.11    Ideal clock and clock with vibration …………………..................	16
Figure 2.12a   The small signal model of a DLL with input noise NI(s)……..…..	16
Figure 2.12b   Bode diagram of Eq.2.8 ……………………………………...…..	17
Figure 2.13a   The small signal model of a DLL with input noise NS (s) ……….	17
Figure 2.13b   Bode diagram of Eq.2.9………………………………………..…	18
Figure 2.14    Tri-state PD (a) Schematic Tri-state (b) state diagram …….…….	19
Figure 2.15    Conceptual schematic of the CP ………………...……………….	20
Figure 2.16    A typical implementation of the CP with the differential scheme 	21
Figure 2.17    Typical delay cells ……………………………………………….	22
Figure 2.18    Register-controlled DLL …………………………………………	25
Figure 2.19    Core part of the register-controlled DLL ………………………...	26
Figure 2.20    Counter-controlled DLL …………………………..……………...	27
Figure 2.21    Block diagram of the SADLL ………………….………………...	28
Figure 2.22    Flowchart of binary search algorithm DLL ……………………...	29
	
Figure 3.1     The DLL in normal lock and false lock conditions ………………	32
Figure 3.2     Two PFDs with separate dead zone …………….………………..	34
Figure 3.3     (a)The DLL architecture (b)The proposed DLL architecture with
              double PFDs………………………….…………………………	35
Figure 3.4     The operations of the proposed DLL architecture. (a) Signal definitions in two PFDs. (b) F lagging R1 and R2. (c) F leading R1 and R2. (d) F falling into the space between R1 and R2 ………	37
Figure 3.5     Block diagram of delay time ……………………………….…….	38
Figure 3.6     Block diagram of front delay cell ……………….…...…………..	39
Figure 3.7     Schematic of startup-controlled circuit associated with PFD...…..	40
Figure 3.8     Timing diagram of startup-controlled circuit ………….………...	40
Figure 3.9     Schematic of the PFD circuit ……………………..……………...	41
Figure 3.10    Schematic of the charge pump circuit ……………….…………...	42
Figure 3.11    Schematic of the delay cell with replica bias ………..…………...	43
Figure 3.12    Schematic transfer curve of the delay line ……………..………...	43
Figure 3.13    Simulated transfer curve of the delay line …………..…………...	45
Figure 3.14    Transient response of control voltage when input =250MHz …....	46
Figure 3.15    Simulated lock time of the DLL when input =250MHz ………....	46
Figure 3.16    Simulated resistance and delay time …………………..………....	47
Figure 3.17    Simulated jitter of the DLL ……………………………………....	47
Figure 3.18    The delay-time and the relative jitter of the proposed DLL.……...	48
Figure 3.19    Measurement setup ……………………………………………....	49
Figure 3.20    Output waveforms of phase 20 (a)250MHz (b) 450MHz……..….	49
Figure 3.21    The jitter performance (a) 250MHz (b) 350MHz ……………......	50
Figure 3.22    The jitter performance (a) 400MHz (b) 450MHz ………..……....	50
Figure 3.23    Output waveforms of phase 20 (a)250MHz (b) 350MHz ………..	51
Figure 3.24    Die photo (a) The DLL (b) proposed the dual-loop DLL ..……....	51
	
Figure 4.1     Architecture of the conventional DLL an d frequency multiplier	55
Figure 4.2     The comparison between output phase and five reference clocks	57
Figure 4.3     The architecture of the proposed DLL-frequency multiplier …….	57
Figure 4.4     Normalized delay of the VCDL in full control voltage ranges …..	58
Figure 4.5     An example of multiple-by-3 frequency ……………………..…..	61
Figure 4.6     Schematic of delay cell ………………………...…………...........	62
Figure 4.7     Schematic of pseudo-differential delay cell …...………….……...	63
Figure 4.8     The up/down circuit in PCC …………………..…………………	63
Figure 4.9     The voltage buffer in PCC ………………………….....................	64
Figure 4.10    Schematic of start-controlled circuit 1 ……….…………………..	65
Figure 4.11    Schematic of start-controlled circuit 2 …………………….……..	66
Figure 4.12    The propose frequency multiplier with the pseudo-differential delay cell inputs ………………………………………………….	67
Figure 4.13    Input and output waveforms of the proposed fast-locking DLL at fin=250MHz ………………………..…………………………....	69
Figure 4.14    A 1.25GHz output with 5xinput frequency of 250MHz ……........69
Figure 4.15    A 2GHz output with 5xinput frequency of 400MHz ………......69
Figure 4.16    The simulated locking time in different corners………………….70
Figure 4.17    The simulated 5xfrequency multiplier indifferent corners………71.
Figure 4.18    The chip layout of the proposed fast-locking DLL-based frequency multiplier ……………………………………………..73
LIST OF TABLES
Table 3.1     Performance summary of the proposed DLL ………….…………..	52
	
Table 4.1     The relationship between the up/down codes and switch signals …	64
Table 4.2     Performance summary of the proposed DLL ………………...……	72
Table 4.3     DLL Performance comparisons ..………………………………….	74

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