本篇論文主要是在描述運用在0.18μm CMOS制程下，設計ㄧ個應用於音頻之極低電壓多位元三角積分調變器。本篇應用於雙取樣技術，始時脈可以被更有效的運用，並減輕運算放大器在設計上的困難。在本篇論文中我們也設計的一個新的低電壓多位元比較器，有別於傳統的電阻分壓法，減少不必要的靜態功率的消耗。
應用於音頻之極低電壓多位元三角積分調變器所達到的SNDR為88dB，而他的動態範圍為89dB，當基頻為22.05KHz，輸入頻率為88dB，而他的動態範圍為89dB，輸入頻率為1.25KHz。當供應電壓為0.8V時，所消耗的能量為4.2mW。

This paper presents a 0.8 V multibit delta-sigma (ΔΣ) modulator with a single switched-opamp (SOP) in a 0.18 μm 1P6M CMOS technology. The double-sampling technique is adopted in the modulator to promote the clock efficiency and relax the requirement of SOP. To improve the accuracy of the multibit quantizer in a low-voltage circumstance and reduce the static power, a new switched-capacitor (SC) multibit quantizer without R-string is proposed.
 The presented ΔΣ modulator achieves a signal-to-noise-plus-distortion ratio (SNDR) of 88 dB and dynamic range (DR) of 89 dB within a 22 kHz of bandwidth under a 1.25MHz of clock rate. The power consumption of the presented modulator is 4.2 mW at a 0.8 V of supply voltage.

Table of Contents
Chapter 1
Introduction.............................................................................................................................1
1.1 Motivation...........................................................................................................................1
1.2 Organization........................................................................................................................2
Chapter 2
Fundamentals of ΔΣ Modulator modulators..........................................................................3
2.1 Introduction.........................................................................................................................3
2.2 Performance Metrics.............................................................................................................4
2.3 Quantization........................................................................................................................6
2.3.1 Quantization Noise......................................................................................................9
2.4 Oversampling....................................................................................................................11
2.5 Noise-shaped ΔΣ Modulator...............................................................................................13
2.5.1 First-Order Noise Shaping.........................................................................................14
2.5.2 Second-order Noise Shaping.....................................................................................17
2.5.3 Higher-order noise shaping.......................................................................................19
2.6 Multibit Quantization ΔΣ modulator..................................................................................21
Chapter 3
The design of low voltage switched-capacitor circuits for ΔΣ modulators........................23
3.1 Introduction.......................................................................................................................23
3.2 Switched-Capacitor Circuits...............................................................................................23
3.3 Low Voltage Switched-Capacitor Circuits.........................................................................24
3.3.1 Voltage Boosting Technique......................................................................................25
3.3.2 Bootstrapped Switch..................................................................................................26
3.4 The Original Switched Opamp Principle............................................................................28
3.5 The Low Voltage Switched Opamp Principle.....................................................................29
3.6 Fully Differential Switched Opamp...................................................................................31
3.6.1 Common Mode Feedback (CMFB)...........................................................................33
3.6.2 Simulation Results.....................................................................................................35
3.6.3 Finite Amplifier Bandwidth and Slew-Rate..............................................................36
3.6.4 Simulation Results.....................................................................................................38
Chapter 4
A Double-Sampling 2nd-Order Multibit ΔΣ Modulator Using A Single Switched-Opamp....................................................................................................................40
4.1 Introduction.......................................................................................................................40
4.2 System Consideration.........................................................................................................41
4.3 Implementation of the Circuit............................................................................................42
4.3.1 Integrator...................................................................................................................43
4.3.2 Multiplexer................................................................................................................46
4.3.3 DAC Feedback..........................................................................................................47
4.3.4 Quantizer...................................................................................................................48
4.4 Dynamic Element Matching...............................................................................................50
4.4.1 Data Weight Average.................................................................................................51
4.5 Clock Generator..................................................................................................................52
4.6 A Second-Order Integrator with DAC Feedback................................................................53
4.7 Simulation Results..............................................................................................................55
4.8 Experimental Results..........................................................................................................57
4.8.1 Input Signal Source and Input Termination Circuit...................................................58
4.8.2 Power Supply and Ground.........................................................................................59
Chapter 5
Conlusions and Future Works...............................................................................................64
5.1 Conclusions.......................................................................................................................64
5.2 Future Works......................................................................................................................64
BIBLIOGRAPHY...................................................................................................................65

List of Figures
Chapter 1
Figure 1.1 Low-voltage switch-capacitor circuit........................................................................1
Figure 1.2 The float switch can be replay be switch opamp......................................................1
Chapter 2
Figure 2.1 Block diagram of a Nyquist-rate ADC......................................................................3
Figure 2.2 Block diagram of an oversampling ADC..................................................................4
Figure 2.3 SNDR versus signal power of an ADC.....................................................................5
Figure 2.4 (a) Two types of quantization midtread.....................................................................6
Figure 2.4 (b) Two types of quantization midrise.......................................................................6
Figure 2.5 (a) Quantizer transfer and quantization error N-bit...................................................7
Figure 2.5 (b) Quantizer transfer and quantization error One-bit...............................................7
Figure 2.6 The comparison of the ideal transfer characteristic and practical
curve for the multi-bit quantization............................................................................................8
Figure 2.7 Quantizer and its linear model..................................................................................9
Figure 2.8 The probability density function of the quantization error.....................................10
Figure 2.9 The power spectral density of the quantization error..............................................10
Figure 2.10 Quantization noise power spectral density............................................................12
Figure 2.11 (a) A general ΔΣ modulator................................................................................13
Figure 2.11 (b) linear model of the ΔΣ modulator.................................................................14
Figure 2.12 First-order ΔΣ modulator......................................................................................15
Figure 2.13 The power spectral density of first order ΔΣ modulator.......................................16
Figure 2.14 Second-order ΔΣ modulator..................................................................................18
Figure 2.15 The power spectral density of the first-order and the second-order noise-shaping...........................................................................................................................19
Figure 2.16 SNR improvements for higher-order modulators.................................................21
Figure 2.17 (a) 3-bit quantizer..................................................................................................21
Figure 2.17 (b) 4-bit quantizer..................................................................................................21
Figure 2.18 SNR improvements for higher-order modulators.................................................22
Chapter 3
Figure 3.1 (a) Delaying discrete-time integrator......................................................................23

Figure 3.1 (b) Clock phase Φ1 and Φ2....................................................................................23
Figure 3.2 Transmission gate composed of NMOS and PMOS...............................................24
Figure 3.3 (a) Switch conductance with VDD=1.8V...............................................................25
Figure 3.3 (b)Switch conductance with VDD=0.8V................................................................25
Figure 3.4 Clock boosting circuit.............................................................................................26
Figure 3.5 Clock bootstrapped switch......................................................................................27
Figure 3.6 Implementation of bootstrapped switch..................................................................27
Figure 3.7 Switched opamp-based integrator...........................................................................28
Figure 3.8 Switched opamp half delay element.......................................................................29
Figure 3.9 The input stage of the switched opamp...................................................................29
Figure 3.10 (a) The modified switched opamp integrator........................................................30
Figure 3.10 (b) The modified switched opamp integrator with double-sampling....................30
Figure 3.11 Schematic of fully differential SOP witch double output stages...........................32
Figure 3.12 The bias circuit......................................................................................................33
Figure 3.13 Dynamic common mode feedback........................................................................34
Figure 3.14 The schematic of the CMFB OTA........................................................................34
Figure 3.15 AC response of the switched opamp.....................................................................35
Figure 3.16 The transient response of the switched opamp with CMFB.................................36
Figure 3.17 The load of the opamp...........................................................................................36
Figure 3.18 Step response.........................................................................................................37
Figure 3.19 AC response of the switched opamp.....................................................................38
Figure 3.20 The transient response of the switched opamp with CMFB.................................38
Chapter 4
Figure 4.1 The architecture of a second-order ΔΣ modulator with a single SOP.....................42
Figure 4.2 A single-loop second-order ΔΣ modulator with a single SOP................................42
Figure 4.3 The first term...........................................................................................................43
Figure 4.4 The second term......................................................................................................43
Figure 4.5 The third term..........................................................................................................44
Figure 4.6 The integrator of the SOP.......................................................................................44
Figure 4.7 (a) Four output states of integrator in four phases..................................................45
Figure 4.7 (b) chopper switches...............................................................................................45
Figure 4.7 (c) The corresponding clocks..................................................................................45
Figure 4.8 The multibit DAC by multiplexer...........................................................................47
Figure 4.9 (a) An eight-level delay-free DAC feedback..........................................................48
Figure 4.9 (b) An eight-level half-delay DAC feedback..........................................................48
Figure 4.10 (a) The comparator for the mulitbit quantizer.......................................................49
Figure 4.10 (b) The SC quantizer.............................................................................................49
Figure 4.11 The DEM...............................................................................................................50
Figure 4.12 Operation of the DWA..........................................................................................51
Figure 4.13 The clock generator...............................................................................................52
Figure 4.14 The simulation results of the clock generator.......................................................52
Figure 4.15 The second order integrator..................................................................................54
Figure 4.16 Input waveform of switched-opamp.....................................................................53
Figure 4.17 The simulation results of integrator outputs..........................................................53
Figure 4.18 The Die photograph of the one-opamp second-order ΔΣ modulator....................55
Figure 4.19 (a) The simulation of the output power spectrum.................................................56
Figure 4.19 (b) The dynamic range of the proposed multibit ΔΣ Modulator...........................56
Figure 4.20 The step environment for measurement................................................................57
Figure 4.21 (a) Photographs of audio precision.......................................................................58
Figure 4.21 (b) Photographs of power supply..........................................................................58
Figure 4.21 (c) Photographs of logic analyzer TLA5201.........................................................58
Figure 4.21 (d) Photographs of arbitrary wareform generator 33250A...................................58
Figure 4.22 Input termination circuit........................................................................................58
Figure 4.23 The regulator circuit..............................................................................................59
Figure 4.24 The reference voltage circuit.................................................................................60
Figure 4.25 The filter tank for the supply voltages..................................................................60
Figure 4.26 The photograph of the experimental DUT board..................................................60
Figure 4.27 (a) Pin configuration diagram...............................................................................61
Figure 4.27 (b) Pin assignments of the chip.............................................................................61
Figure 4.28 The Die photograph...............................................................................................62
Figure 4.29 Measured output power sptctrum..........................................................................62
List of Tables
Table 3.1 Performance summary of simulation results of switched opamp.............................39
Table 4.1 The corresponding table of exchanged thermometer code.......................................46
Table 4.2 The performance summary of the proposed 0.8 V multibit ΔΣ Modulator..............56
Table 4.3 The performance summary of the proposed 0.8 V multibit ΔΣ Modulator..............63

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