隨著積體電路的製程技術不斷的演進，截至目前業已進入了奈米製程。然而在類比電路的設計與實現上卻沒有明顯受益，肇因於臨界電壓並未顯著減少。而製程的不斷演進，閘極的崩潰電壓持續降低，所以電源電壓也需要相對地減少。因此低電壓電路技術的發展有愈來愈急迫的需要。且低電壓電路技術能更有效地縮小電池的體積及重量，而這才符合可攜式個人無線電子通信產品之輕薄短小和電池等長時效性等要求。
因為製程的進步與架構的更新，所以寬頻上之應用也愈來愈多。而本篇論文所研究應用的頻寬則是設計並且實現應用於對稱性數位用戶專線(Asymmetric Digital Subscribe Line，ADSL)。 ADSL是現時一般社會大眾所廣泛運用的網路連線方式，目前全球ADSL用戶數量仍在迅速成長，為了刺激ADSL的持續成長，市場需要低成本、高效能的ADSL積體電路，就成本來考量ADSL，若能將各種元件整合在一起便是類比前端（Analog Front End，AFE）成功的關鍵，也就是所謂SOC的概念(System on Chip)。數位電路的製程會因為製程的進展而改善，然而類比電路的設計卻因為諸多的因素無法隨著製程演進而有相對大幅度的改良。而在本論文中則研究與設計能夠在低電壓中仍能正常運作之類比數位轉換器，以利於能夠與數位電路更密切的整合。
本論文提出之低電壓寬頻三角積分調變器，是運用二種架構所組成之多級串疊架構。第一級的架構是運用低雜訊架構，而第二級則是傳統之多級回授架構。而每級分別能提供兩階的雜訊移頻，所以整體系統能夠提供四階的雜訊移頻。且採用了雙取樣技術以增進時脈效益並紓緩運算放大器之規格需求。而所提出之調變器已於0.13微米1P8M標準製程實現，於ADSL之應用頻寬1.1 MHz下，時脈頻率為20MHz，其最大之訊號雜訊比可達到 79.390 dB 動態範圍更可達到 82.103 dB。而在僅只0.8伏特之供應電壓之下，整體的消耗功率只有15.7毫瓦。

With the improvement of the process of the integrated circuit, nanometer technology is applied. However it is not benefited greatly to design and implement the analog circuit due to the threshold voltage is less decreased. Due to the improvement of the process, the power supply has to decrease in proportion to the breakdown voltage of the gate. The requirement of the low voltage circuit design is getting bigger and bigger. The low voltage circuit design can effectively reduce the volume and weight of the battery. It satisfies the portability and the battery life of the portable wireless communications products.
The improvement of the process and architecture, the wideband applications grow up greatly. ADSL is one of the most popular methods of the internet connection. The number of the ADSL users is increasing quickly. In order to improve the development of ADSL, low cost and high performance IC is required. In mention of the cost, the key point to implement an efficient AFE is how to integrate each element effectively. It is the concept of SOC. Digital IC get advance due to the process improvement, but analog IC do not. In this thesis, we discuss and design the ADC work in low supply voltage to integrate with the digital integrated circuit more compactly.
We present a low voltage wideband delta-sigma modulator. The MASH architecture is combined with two structures. The first stage is low distortion structure and the second stage is traditional feedback one. Each stage performs second-order noise shaping, and the entire system can accomplish fourth-order noise shaping. Double sampling is used to promote the clock efficiency and relax the requirement of the opamps. The proposed modulator has been implemented in a 0.13

CHAPTER 1	INTRODUCTION	1
1.1	Motivation	1
1.2	Organization	2
CHAPTER 2	FUNDAMENTALS OF DS MODULATOR	3
2.1	Introduction	3
2.2	Performance Metrics	4
2.2.1	Resolution	4
2.2.2	Signal-to-Noise Ratio (SNR)	4
2.2.3	Signal-to-Noise plus Distortion Ratio (SNDR)	5
2.2.4	Spurious Free Dynamic Range (SFDR)	5
2.2.5	Dynamic Range (DR)	5
2.3	Quantization	6
2.3.1	Single-bit Quantization	6
2.3.2	Multi-bit Quantization	8
2.3.2.1	Mid-rise Quantizer	8
2.3.2.2	Mid-tread Quantizer	9
2.3.2.3	Nonidealities of the Multi-bit Quantizer	9
2.3.3	Quantization Error	10
2.4	Oversampling Technique	12
2.5	Noise Shaped DS Modulator	13
2.5.1	First Order Noise Shaping	14
2.5.2	Second-Order Noise Shaping	17
2.5.2.1	Traditional Topology	17
2.5.2.2	Low Distortion Topology	19
2.5.3	Higher Order Noise Shaping	20
2.5.3.1	Single Loop Topology	21
2.5.3.2	Cascaded Topology	21
2.6	Multibit Quantization	23
2.6.1	Multibit Quantization in Traditional Topology	23
2.6.2	Multibit Quantization in Low Distortion Topology	23
2.6.2.1	Switch Capacitor Summing	24
2.6.2.2	Summer Opamp	24
2.6.2.3	Charge Sharing	25
CHAPTER 3	THE DESIGN OF LOW VOLTAGE CIRCUITS FOR DS MODULATOR			27
3.1	Introduction	27
3.2	Low Voltage Design	27
3.2.1	Low Threshold Voltage Process	29
3.2.2	Voltage Boosting	29
3.2.2.1	Clock Boosting	30
3.2.2.2	Bootstrapped Switch	30
3.2.2.3	Bootstrapped Switch as a Sampling Switch	31
3.3	Switched-Capacitor Circuit	32
3.3.1	Inverting Integrator	32
3.3.2	Non-Inverting Integrator	33
3.4	The Switched Opamp Principle	34
3.4.1	Fully Differential Switched Opamp	37
3.4.2	Common Mode Feedback (CMFB)	37
3.4.3	Bias Circuit	39
3.5	Multibit Quantizer	39
3.5.1	Low Voltage Multibit Quantizer	40
3.5.2	Low Voltage Comparator	41
3.6	Dynamic Element Matching (DEM)	42
3.6.1	Data Weighted Averaging (DWA)	42
3.7	Non-Overlapped Clock Generator	43
3.8	Cascaded DS Modulator	44
3.8.1	Implementation of the Cascaded DS Modulator	45
CHAPTER 4	A FOURTH ORDER 2-2 CASCADED DS MODULATOR	49
4.1	Introduction	49
4.2	Elements Implementation	49
4.2.1	Bootstrapped Switch	50
4.2.2	Comparator	51
4.2.3	Multibit Quantizer	52
4.2.4	Switched Opamp	52
4.2.5	Integrator	54
4.3	Architecture Simulation	55
4.3.1	Behavioral Simulation	55
4.3.2	Transistor Level Simulation	57
4.3.2.1	A Second Order Low Distortion Topology DS Modulator	57
4.3.2.2	A Second Order Traditional Topology DS Modulator	58
4.3.2.3	A Fourth Order Cascaded DS Modulator	59
4.4	Experimental Results	61
4.4.1	Input Termination Circuit	62
4.4.2	Regulator Circuit	63
4.4.3	Reference Voltage Generator	64
4.4.4	Filter Tank	64
4.4.5	Pin Assignment and DUT Board	65
4.5	Summary	66
CHAPTER 5	CONCLUSIONS	69
5.1	Conclusions	69
5.2	Future Works	70
BIBLIOGRAPHY	71


List of Figures

Chapter 2
Figure 2.1 Block diagram of a conventional ADC	3
Figure 2.2 Block diagram of a oversampling ADC	4
Figure 2.3 SNDR / SNR versus input power	5
Figure 2.4 Single-bit quantization and the quantization error	7
Figure 2.5 The practical transfer curve	7
Figure 2.6 Mid-rise quantization and the quantization error	8
Figure 2.7 Mid-rise quantization and the quantization error	9
Figure 2.8 The nonlinearities of the practical multi-bit quantizer	10
Figure 2.9 The probability density function of the quantization error	11
Figure 2.10 The converter with oversampling technique without noise shaping	12
Figure 2.11 The power spectral density of the quantization error after the lowpass filter	12
Figure 2.12 The architecture of th DS modulation	13
Figure 2.13 The block diagram of the DS modulation	14
Figure 2.14 The linear model of the first-order DS modulator	15
Figure 2.15 Linear model of the second-order DS modulator with traditional topology	17
Figure 2.16 The PSD of the first order and the second order noise shaping	18
Figure 2.17 Linear model of the second-order DS modulator with low distortion topology	19
Figure 2.18 The performance prediction with OSR and Lth order DS modulator	21
Figure 2.19 A simplified architecture of cascaded modulator	22
Figure 2.20 Switch capacitor summing	24
Figure 2.21 Summer opamp	25
Figure 2.22 Charge sharing	26

Chapter 3
Figure 3.1 Transmission gate in low supply voltage	28
Figure 3.2 The conductances of the switches under differential processes	28
Figure 3.3 The conductance of the switches under 0.8V of supply voltage	28
Figure 3.4 Clock boosting technique	30
Figure 3.5 Bootstrapped switch	31
Figure 3.6 Bootstrapped switch as a sampling Switch	32
Figure 3.7 Inverting integrator	33
Figure 3.8 Non-inverting integrator	34
Figure 3.9 The SC circuit which has removed the floating switches	34
Figure 3.10 The switched opamp based integrators.	35
Figure 3.11 The full delay integrator	35
Figure 3.12 The modified switched opamp integrator	36
Figure 3.13 The fully differential switched opamp	37
Figure 3.14 The common mode feedback circuit	38
Figure 3.15 The core opamp of the common mode feedback circuit	39
Figure 3.16 The bias circuit	39
Figure 3.17 Switched capacitor based multibit quantizer	40
Figure 3.18 Four input multibit quantizer	40
Figure 3.19 Multibit quantizer without resistors	41
Figure 3.20 The low voltage comparator with a SR-latch	42
Figure 3.21 The operation principle of the DWA	43
Figure 3.22 The non-overlapped clock generator	43
Figure 3.23 The block diagram of the cascaded DS modulator	44
Figure 3.24 The schematic of the first stage of the 2-2 cascaded DS modulator	47
Figure 3.25 The schematic of the second stage of the 2-2 cascaded DS modulator	48

Chapter 4
Figure 4.1 FFT simulation model	50
Figure 4.2 The transient simulation of the bootstrapped switch	50
Figure 4.3 The FFT power spectrum of the simulation model	51
Figure 4.4 Simulation of hysteresis and offset	51
Figure 4.5 Simulation of the proposed multibit quantizer	52
Figure 4.6 Simulation of frequency response of the SOP	53
Figure 4.7 Simulation of output swing	53
Figure 4.8 Simulation of DC gain nonlinearity	53
Figure 4.9 The transient response of the integrator with double sampling	54
Figure 4.10 The behavioral simulation model	56
Figure 4.11 The output swing of the integrators	56
Figure 4.12 The power spectrum of the behavioral simulation model	56
Figure 4.13 The DR of the behavioral simulation model	57
Figure 4.14 The power spectrum of the first stage	58
Figure 4.15 The power spectrum of the second stage	58
Figure 4.16 The transient response of the IO of each integrator	59
Figure 4.17 The power spectrum of the proposed 2-2 cascaded DS modulator	60
Figure 4.18 The SNR and SNDR vs. input power	60
Figure 4.19 The physical layout of the proposed DS modulator	60
Figure 4.20 The experimental test setup environment	61
Figure 4.21 The input termination circuit	63
Figure 4.22 The regulator circuit for supply voltage	63
Figure 4.23 The reference voltage generator circuit	64
Figure 4.24 The filter tank circuit	65
Figure 4.25 The die photograph of the proposed DS modulator	65
Figure 4.26 The pin configuration diagram and pin assignment	66
Figure 4.27 The photograph of the DUT board for measurement	66
Figure 4.28 FOM vs. power supply voltage and power vs. power supply voltage	68


List of Tables

Chapter 4
Table 4.1 The performance summary of the proposed SOP	54
Table 4.2 The performance summary of the presented DS modulator	61
Table 4.3 The performance comparison with other literatures published	67

[1]	J. Silva, U. K. Moon, J. Steensgaard, and G. C. Temes, “Wideband Low-Distortion Delta Sigma ADC Topology,” Electron. Lett., vol. 37, pp. 737-738, Jun. 2001.
[2]	R. Schreier, and G. C. Temes, “Understanding Delta-Sigma Data Converters,” IEEE Press Wiley Interscience 2005. 
[3]	K. Nam, et al, “A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion,” IEEE J. Solid-State Circuits, vol. 40, pp. 1855-1864, Sept. 2005.
[4]	G. Ahn, D. Chang, M. Brown, N. Ozaki, H. Youra, K. Hamashita, K. Takasuka, G. Temes, and U. K. Moon, “0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators,” IEEE J. Solid-State Circuits , vol. 40, no. 12, pp. 2398-2461, Dec. 2005.
[5]	M. Keskin, “A low-voltage CMOS switch with a novel clock boosting scheme,” IEEE Trans. Circuits Syst. II, vol. 52, pp. 185–188, Apr. 2005.
[6]	M. G. Kim, G. C. Ahn, P. K. Hanumolu, S. H. Lee, S. H. Kim, S. B. You, J. W. Kim, G. C. Temes and U. K. Moon, “A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC,” IEEE J. Solid-State Circuits, vol. 43, pp. 1195-1206, May 2008.
[7]	M. Dessouky and A. Kaiser, “A 1V 1mW digital-audio modulator with 88dB dynamic range using local switch bootstrapping,”in Proc. CICC, 2000, pp. 13–16.
[8]	A. M. Abo, P. R. Gray, “A 1.5V, 10-bit, 14-MS/s CMOS pipeline analog-to-digital converter, ” IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May 1999.
[9]	M. Dessouky, A. Kaiser, “Input switch configuration for rail-to-rail operation of switches opamp circuits,” Electron Letters, vol. 35, no. 1, pp8-10, Jan. 1999.
[10]	M. Steyaert, J. Crols, and S. Gogaert, “Switched opamp, a technique for realizing full CMOS switched-capacitor filters at very low voltages,” in Proc. 19th Eur. Solid-State Circuits Conf., Sept. 1993, pp. 178–181.
[11]	J. Crols and M. Steyaert, “Switched opamp, an approach to realize full CMOS switched-capacitor circuits at very low power supply voltage,” IEEE J. Solid-State Circuits, vol. 29, pp. 936-942, Aug.1997.
[12]	C. H. Kuo and S. I. Liu, “A 1-V 10.7MHz fourth-order bandpass modulators using two switched opamps,” IEEE J. Solid-State Circuits, vol. 39, no. 11, Nov. 2004.
[13]	T. Salo, S. Lindfors, and K. A. I. Halonen, “A double-sampling SC-resonator for low voltage bandpass Delta Sigma modulators,” IEEE Trans. Circuits Syst. II, vol.49, no. 12, pp. 737-747, Dec. 2002.
[14]	S. Y. Lee, S.C. Lee, and Y. M. Tsai, ‘Design of low-power low-voltage switched-opamp based bandpass filter for microstimulator’, IEEE Ref. 10 Conference,, vol. D, pp. 282-285 vol.4, Nov. 2004.
[15]	M. Waltari and K. Halonen, “Fully differential switched opamp with enhanced common mode feedback,” Electron Letters, vol. 34, . no. 23, 12th, pp. 8-10, Jan. 1998.
[16]	M. Waltari and K. Halonen, “A Switched-Capacitor with Fast Common Mode Feedback,” The 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS, vol. 3, pp. 1523-1525, 1999.
[17]	R. J. Van de Plassche and D. Goedhart, ‘A monolithic 14-bit D/A converter’, IEEE J. Solid-State Circuits, vol. SC-14, no. 3, pp. 552-556, Jan. 1979.
[18]	Keady and C.Lyden, “Tree structure for mismatch noise-shaping multi-bit DAC,” Electronics Letters, vol. 33, no. 17, pp. 1431-1432, 1994.
[19]	R. T. Baird and T. S. Fiez, “Linearity enhancement of multi-bit delta sigma A/D and D/A converters using data weighted averaging,” IEEE Trans. Circuits Syst. II, vol. 42, pp. 753–762, Dec. 1995.
[20]	H. Leung, ‘Architectures for multibit oversampled A/D converter employing dynamic element matching techniques’ in Proc. International Symposium on Circuits and Systems, pp. 1657-1660,1991.
[21]	R. Gaggl, M. Inversi, and A. Wiesbauer, “A power optimized 14-bit SC DS modulator for ADSL CO applications,” in Proc. IEEE ISSCC’04, pp. 82–514, Feb. 2004.
[22]	R. Reutemann, P. Balmelli, and Q. Huang, “A 33-mW 14b 2.5-MSamples/s, DS A/D converter in 0.25-um digital CMOS,” in Proc. IEEE ISSCC’02, pp. 316–470, Feb. 2002.
[23]	I. Fujimori et al., “A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8x oversampling,” IEEE J. Solid-State Circuits, vol. 35, pp. 1820–1828, Dec. 2000.
[24]	M. Safi-Harb and G.W. Roberts, “Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 52, no. 10, pp. 2075–2089, Oct. 2005.
[25]	P. Balmelli, H. Qiuting, and F. Piazza, “A 50-mW 14-bit 2.5 MS/s, DS modulator in CMOS 0.25um digital CMOS technology,” in Proc. IEEE Symp. VLSI Circuits, pp. 142–143, Jun. 2000.
[26]	S. K. Gupta, T. L. Brooks, and V. Fong, “A 64MHz DS ADC with 105 dB IM3 distortion using a linearized replica sampling network,” in Proc. IEEE ISSCC’02, pp. 224–462, Feb. 2002.
[27]	R. del R o, J. M. de la Rosa, B. P rez-Verd , M. Delgado-Restituto, R. Dominguez-Castro, F. Medeiro, and A. Rodr guez-Vasquez, “Highly linear 2.5-V CMOS    modulator for ADSL+,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 51, no. 1, pp. 47–62, Jan. 2004.
[28]	Y. Geerts, A. M. Marques, M. Steyaert, andW. Sansen, “A 3.3-V, 15-bit, delta–sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications,” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 927–936, Jul. 1999.
[29]	R. del Rio et al., “Top-down design of a xDSL 14-bit 4-MS/s sigma-delta modulator in digital CMOS technology,” in Proc. Design, Automation Test in Europe Conf., pp. 348–351, Mar. 2001.
[30]	M. Keskin, U, K, Moon, and Gabor. C. Temes, “A 1-V 10-MHz clock-rate 13-Bit CMOS delta sigma modulator using unity-gain-rest opamps,” IEEE J. Solid-state Circuit, vol. 37, no, 7, pp. 817-842, Jul. 2002.