本論文旨在探討將智慧型控制器透過混合數字系統之硬體架構實現於FPGA平台，並探討算術表示對於控制器計算效能的影響，同時套用TS-CMAC控制器模擬與實現；目的是透過Altera SOPC與NIOS II處理器的使用者指令集實現32位元混合數字系統處理器，並應用於TS-CMAC作為算術運算。其中，控制器的計算性能優劣取決於算術表示；然而，控制器實作上必須考量到所需要花費的FPGA邏輯元件成本，以及數字精度的影響，以上因素均會影響控整器整體效能之呈現；因此，本論文所提出的混合數字系統硬體化系統架構旨在解決以上問題。硬體化系統架構有以下三個優點： i) 低花費的FPGA邏輯元件； ii) 高運算效能； iii) 高精度的算術運算。經由實驗結果得知，透過混合數字系統能有效提升TS-CMAC的算術運算速度，同時在設計算術硬體上減少佔用面積並保有高數字精確度，達到TS-CMAC在控制上之準確性。

In this paper, we developed a hardware intelligent controller, such as TS-CMAC, implemented on a field programmable gate array (FPGA) platform. We also discuss the impact of arithmetic representation on computing performance of controller. In addition, we implemented a 32-bit hybrid number system processor for TS-CMAC arithmetic operations. However, arithmetic representations for intelligent controller is dependent on computing performance. The tradeoff between precision and representation along with FPGA logic element costs requirements are considered. Therefore, our hardware system architecture seek to fill the gap between why. We proposed hybrid number system for our controller arithmetic representation. The hardware system architecture has advantages: i) low costs of hardware logic element; ii) high computing performance; iii) high accuracy of arithmetic operation. According to experimental results, TS-CMAC arithmetic operation speed can be increased effectively by hybrid number system which can not only reduce area occupied of hardware but also maintain high precision in arithmetic hardware design, and thus enhance TS-CMAC accuracy in intelligent control .

Table of Contents
Abstract in Chinese I
Abstract in English II
Table of Contents III
List of Figures VI
List of Tables VIII
1 INTRODUCTION 1
1.1 Research Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Problem Formulation and Motivations . . . . . . . . . . . . . . . . . . 4
1.4 Organization of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 HYBRID NUMBER SYSTEM 7
2.1 Floating-Point Number System . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Floating-Point Arithmetic Overview . . . . . . . . . . . . . . . . 8
2.1.2 Multiplication Algorithms . . . . . . . . . . . . . . . . . . . . . 11
2.1.3 Addition and Subtraction Algorithms . . . . . . . . . . . . . . . 14
2.1.4 Division Algorithms . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Logarithmic Number System . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.1 Logarithmic Arithmetic Overview . . . . . . . . . . . . . . . . . 20
2.2.2 Multiplication and Division Algorithms . . . . . . . . . . . . . . 22
2.2.3 Addition and Subtraction Algorithms . . . . . . . . . . . . . . . 24
2.2.4 Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3 Conversion Algorithms of Format . . . . . . . . . . . . . . . . . . . . . 28
2.3.1 Design of Logarithm to Floating-Point . . . . . . . . . . . . . . 28
2.3.2 Design of Floating-Point to Logarithm . . . . . . . . . . . . . . 31
2.3.3 The Error of Conversion Algorithm . . . . . . . . . . . . . . . . 32
2.4 Exponential Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4.1 Exponential Algorithm . . . . . . . . . . . . . . . . . . . . . . . 33
3 OVERALL SYSTEM ARCHITECTURE AND ITS DESIGN 35
3.1 NIOS II Software Development Environment . . . . . . . . . . . . . . . 35
3.2 Altera SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3 Custom Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3.1 Custom Instructions of Arithmetic Operation . . . . . . . . . . 38
3.4 Takagi-Sugeno Fuzzy Cerebellar Model Articulation Controller . . . . . 40
3.4.1 Cerebellar Model Articulation Controller . . . . . . . . . . . . . 40
3.4.2 Takagi-Sugeno Fuzzy Theory . . . . . . . . . . . . . . . . . . . . 42
3.4.3 CMAC with T-S fuzzy model . . . . . . . . . . . . . . . . . . . 43
3.5 Overall System Structure of TS-CMAC . . . . . . . . . . . . . . . . . 47
3.6 Overall System Architecture . . . . . . . . . . . . . . . . . . . . . . . . 47
4 VERIFICATION AND EXPERIMENTAL RESULTS 49
4.1 Hardware Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 Hardware Costs and Experimental Results . . . . . . . . . . . . . . . . 52
4.2.1 Hardware Consumption of Logic Element . . . . . . . . . . . . . 52
4.2.2 Delay Time and Clock Cycle . . . . . . . . . . . . . . . . . . . . 54
5 CONCLUSIONS AND FUTURE OUTLOOK 57
5.1 Research Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.2 Future Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Reference Materials 59

List of Figures
2.1 Hybrid number system architecture . . . . . . . . . . . . . . . . . . . . 7
2.2 IEEE 754 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 FLP representable number range diagram . . . . . . . . . . . . . . . . 10
2.4 FLP multiplication flow chart . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Structure of FLP multiplication . . . . . . . . . . . . . . . . . . . . . . 13
2.6 FLP addition and subtraction flow chart . . . . . . . . . . . . . . . . . 15
2.7 Structure of FLP addition . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8 Structure of FLP subtraction . . . . . . . . . . . . . . . . . . . . . . . 17
2.9 Structure of FLP division . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.10 32-bit single precision LNS format . . . . . . . . . . . . . . . . . . . . . 20
2.11 Structure of LNS multiplication . . . . . . . . . . . . . . . . . . . . . . 23
2.12 Structure of LNS division . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.13 LNS addition and subtraction of f (k) . . . . . . . . . . . . . . . . . . . 26
2.14 Structure of LNS addition and subtraction . . . . . . . . . . . . . . . . 27
2.15 The hardware architecture of LNS-to-FLP conversion . . . . . . . . . . 30
2.16 The hardware architecture of FLP-to-LNS conversion . . . . . . . . . . 32
2.17 The conversion errors between the FLP-to-LNS and LNS-to-FLP . . . . 33
2.18 Exponential function diagram . . . . . . . . . . . . . . . . . . . . . . . 34
3.1 SOPC builder flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2 NIOS Embedded Processor . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3 Custom instruction library . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4 Importation of hardware design from custom instructions . . . . . . . . 39
3.5 CMAC basic architecure . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.6 CMAC separate each input from each memory region . . . . . . . . . . 42
3.7 CMAC architecture using T-S fuzzy model . . . . . . . . . . . . . . . 44
3.8 TS-CMAC algorithm with hybrid number system overall system architecture
hardware design . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.9 Hardware design of overall system architecture on SOPC . . . . . . . . 48
4.1 Each of custom instructions LEs consumption diagram . . . . . . . . . 53
4.2 Each of custom instructions delay time diagram . . . . . . . . . . . . . 55
4.3 Each of custom instructions clock cycle diagram . . . . . . . . . . . . . 56

List of Tables
2.1 Expression of IEEE-754 and exception . . . . . . . . . . . . . . . . . . 10
3.1 Importation of hardware design from custom instructions . . . . . . . . 39
4.1 Arithmetic operation verification of software and hardware . . . . . . . 51
4.2 Custom instruction LEs consumption . . . . . . . . . . . . . . . . . . . 52
4.3 Custom instruction delay time . . . . . . . . . . . . . . . . . . . . . . . 54
4.4 Custom instruction clock cycle . . . . . . . . . . . . . . . . . . . . . . . 56

Reference Materials
[1] F. Fons, M. Fons, and E. Canto, “Hardware-software co-design of a dynamically reconfigurable fpga-based fuzzy logic controller,” in Electronics, Circuits and Systems, 2006. ICECS ’06. 13th IEEE International Conference on, Dec 2006, pp. 1228–1231.
[2] S. Jung and S. S. Kim, “Hardware implementation of a real-time neural network controller with a dsp and an fpga for nonlinear systems,” Industrial Electronics, IEEE Transactions on, vol. 54, no. 1, pp. 265–271, Feb 2007.
[3] J. Mooney, A. Mahdi, and M. Halton, “Application-specific instruction-set processor for control of multi-rail dc-dc converter systems,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 60, no. 1, pp. 243–254, Jan 2013.
[4] A. Sathyan, N. Milivojevic, Y.-J. Lee, M. Krishnamurthy, and A. Emadi, “An fpga-based novel digital pwm control scheme for bldc motor drives,” Industrial Electronics, IEEE Transactions on, vol. 56, no. 8, pp. 3040–3049, Aug 2009.
[5] J. S. Lee, B. H. Lee, B.-S. Kang, and Y.-H. Kim, “An application specific processor-based controller for plasma display panels,” Consumer Electronics, IEEE Transactions on, vol. 52, no. 3, pp. 953–961, Aug 2006.
[6] A. Savich, M. Moussa, and S. Areibi, “The impact of arithmetic representation on implementing mlp-bp on fpgas: A study,” Neural Networks, IEEE Transactions on, vol. 18, no. 1, pp. 240–252, Jan 2007.
[7] A. Gomperts, A. Ukil, and F. Zurfluh, “Development and implementation of parameterized fpga-based general purpose neural networks for online applications,” Industrial Informatics, IEEE Transactions on, vol. 7, no. 1, pp. 78–89, Feb 2011.
[8] D. Goldberg, “What every computer scientist should know about floating-point arithmetic,” ACM Computing Surveys (CSUR), vol. 23, no. 1, pp. 5–48, 1991. 
[9] Y. C. Lei and C. H. Lin, “Dsp architecture with jumping-floating-point number system,” in Asian Solid-State Circuits Conference, 2005, Nov 2005, pp. 405–408.
[10] Y. Hagiwara, Y. Kita, T. Miyamoto, Y. Toba, H. Hara, and T. Akazawa, “A single chip digital signal processor and its application to real-time speech analysis,” Solid-
State Circuits, IEEE Journal of, vol. 18, no. 1, pp. 91–99, 1983.
[11] F. Taylor, “A reconfigurable binary/rns/lns architecture for dsp,” in Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP ’87.,
vol. 12, Apr 1987, pp. 503–506.
[12] C. Turner, “A fast binary logarithm algorithm [dsp tips tricks],” Signal Processing Magazine, IEEE, vol. 27, no. 5, pp. 124–140, Sept 2010.
[13] M. Haselman, M. Beauchamp, A. Wood, S. Hauck, K. Underwood, and K. Hemmert, “A comparison of floating point and logarithmic number systems for fpgas,” in Field-Programmable Custom Computing Machines, 2005. FCCM 2005. 13th Annual IEEE Symposium on, April 2005, pp. 181–190.
[14] J. N. Coleman and E. I. Chester, “A 32 bit logarithmic arithmetic unit and its performance compared to floating-point,” in Computer Arithmetic, 1999. Proceedings. 14th IEEE Symposium on, 1999, pp. 142–151.
[15] F.-S. Lai and C.-F. Wu, “A hybrid number system processor with geometric and complex arithmetic capabilities,” Computers, IEEE Transactions on, vol. 40, no. 8, pp. 952–962, 1991.
[16] V. Paliouras, “Optimization of lns operations for embedded signal processing applications,” in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium
on, vol. 2, 2002, pp. II–744–II–747 vol.2.
[17] E. Swartzlander, D. Chandra, H. Nagle, and S. Starks, “Sign/logarithm arithmetic for fft implementation,” Computers, IEEE Transactions on, vol. C-32, no. 6, pp.
526–534, June 1983.
[18] G. Sicuranza, “On efficient implementations of 2-d digital filters using logarithmic number systems,” Acoustics, Speech and Signal Processing, IEEE Transactions
on, vol. 31, no. 4, pp. 877–885, Aug 1983.
[19] Q. N. Le and J.-W. Jeon, “Neural-network-based low-speed-damping controller for stepper motor with an fpga,” Industrial Electronics, IEEE Transactions on, vol. 57, no. 9, pp. 3167–3180, Sept 2010.
[20] J. D. Leroux, M.-A. Tetrault, D. Rouleau, C. Pepin, J. B. Michaud, J. Cadorette, R. Fontaine, and R. Lecomte, “Time discrimination techniques using artificial neural networks for positron emission tomography,” Nuclear Science, IEEE Transactions on, vol. 56, no. 3, pp. 588–595, June 2009.
[21] D. Zhang and H. Li, “A stochastic-based fpga controller for an induction motor drive with integrated neural network algorithms,” Industrial Electronics, IEEE Transactions on, vol. 55, no. 2, pp. 551–561, Feb 2008.
[22] H.-C. Huang and C.-C. Tsai, “Fpga implementation of an embedded robust adaptive controller for autonomous omnidirectional mobile platform,” Industrial Electronics,
IEEE Transactions on, vol. 56, no. 5, pp. 1604–1616, May 2009.
[23] F. Taeed, Z. Salam, and S. Ayob, “Fpga implementation of a single-input fuzzy logic controller for boost converter with the absence of an external analog-to-digital converter,” Industrial Electronics, IEEE Transactions on, vol. 59, no. 2, pp. 1208–1217, Feb 2012.
[24] T.-S. Chiang and C.-S. Chiu, “Ts-cmac based sliding mode control for time-delay systems,” in Fuzzy Systems, 2006 IEEE International Conference on, 2006, pp. 1918–1923.
[25] F. Taylor, “A hybrid floating-point logarithmic number system processor,” Circuits and Systems, IEEE Transactions on, vol. 32, no. 1, pp. 92–95, Jan 1985.
[26] B. Parhami, Computer arithmetic: algorithms and  hardware designs. Oxford University Press, Inc., 2009.
[27] D. DasSarma and D. Matula, “Measuring the accuracy of rom reciprocal tables,” Computers, IEEE Transactions on, vol. 43, no. 8, pp. 932–940, Aug 1994.
[28] C. Chen, R.-L. Chen, and C.-H. Yang, “Pipelined computation of very large word-length lns addition/subtraction with polynomial hardware cost,” Computers, IEEE Transactions on, vol. 49, no. 7, pp. 716–726, Jul 2000.
[29] M. Arnold, T. Bailey, and J. Cowles, “Comments on ”an architecture for addition and subtraction of long word length numbers in the logarithmic number system” by d.m. lewis,” Computers, IEEE Transactions on, vol. 41, no. 6, pp. 786–788, June 1992.
[30] M. Arnold, “A risc processor with redundant lns instructions,” in Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on, 2006, pp. 475–482.
[31] M. Combet, H. Van Zonneveld, and L. Verbeek, “Computation of the base two logarithm of binary numbers,” Electronic Computers, IEEE Transactions on, vol. EC-14, no. 6, pp. 863–867, Dec 1965.
[32] E. L. Hall, D. Lynch, and I. Dwyer, S.J., “Generation of products and quotients using approximate binary logarithms for digital filtering applications,” Computers,
IEEE Transactions on, vol. C-19, no. 2, pp. 97–105, Feb 1970.
[33] P.-T. P. Tang, “Table-driven implementation of the exponential function in ieee floating-point arithmetic,” ACM Transactions on Mathematical Software (TOMS), vol. 15, no. 2, pp. 144–157, 1989.
[34] S. Altera, “Builder user guide.(2010, december).”
[35] I. Nios, “Custom instruction user guide,” 2007.
[36] T. Takagi and M. Sugeno, “Fuzzy identification of systems and its applications to modeling and control,” Systems, Man and Cybernetics, IEEE Transactions on, no. 1, pp. 116–132, 1985.