為了測試一複雜的系統單晶片(System-on-Chip)，晶片內部所使用的矽智產(IP)應該在設計階段時就考慮測試方法，考慮Design-For-Testability(DFT)。內嵌在SOC中的IP或整合者自行加入的電路單元，接稱為一個core。Test-Access-Mechanism(TAM)是將測試向量(Test Vectors)以及控制訊號(control signals)經由SOC pins傳送至內嵌的cores，並將測試結果(response)輸出至SOC pins。目前在TAM的設計上大都是採用Scan-based的方式，但是採此方式在移位測試向量與測試結果時需花費大量時間，所以TAM的結構設計與cores的測試排程接影響到測試的時間，反映在該SOC測試成本上。因此，在設計TAM時，我們皆是希望最後的測試時間能越短越好。    我們設計TAM的方法是以”可重新配置之多重輸入串架構(Reconfigurable Multiple Scan Chain, RMSC)”為基礎的設計方法。若採用並行(Concurrent)測試排程，SOC中不同的core會串一起，分享相同的掃描鏈(Scan-Chain)並同時進行測試。但是，在同一個SOC中，針對core不同，該測試向量的數量(Test Length)也不一樣，所以core完成測試的時間也不盡相同。Test Length較少的cores會提早結束測試，但其他的cores仍然需要輸入及輸出測試資料，所以針對已經結束測試的core將會輸入Don’t-Care的資料，使針對其他尚未完成測試的core能繼續些收到測試資料。RMSC則市針對此問題的解決方法，利用新增的控制訊號以及多功器將以完成測試的cores旁路(Bypass)，如此就不用輸入Don’t-Care的資料，對大的好處就是每完成一個core，整個掃描鏈的長度也會下降，位移測試向量與結果的cycle數減少，進而縮短測試時間。    採用RMSC架構的TAM，若是SOC內嵌的cores數量太龐大，相對的需要的控制訊號也會增多。增加多的控制訊號，需要增加多的SOC chip面積以及SOC pins，在實際的考量底下，所能採用的控制訊號數量將會變成一個限制，於是，在整個SOC測試排程上，何處要使用控制訊號，何處填補Don’t-Care資料將決定TAM的設計，也決定測試的時間長短。若要完全將所有可能的控制訊號組合都嘗試運算，那將花費大量的時間，且運算時間與控制訊號的數量呈指數成長，所以控制訊號的挑選方法必須更有效率。在此，我們提出了一個新的演算法來挑選控制訊號。首先，我們先利用以單一core做TAM分配為模型，計算出粗略的Shift-Cycle建立矩陣，利用矩陣運算依能省最多的控制訊號優先挑選。因挑選的控制訊號只是粗略建模計算出來的，或許非最佳的控制訊號組合，在此我們會多選數個訊號做排列組合，以求出最佳或考進最佳的解。    借由RMSC的架構，可以有效的縮短測試時間，搭配我們提出的控制訊號演算法，更可以縮短在設計時的運算時間，進而下降測試本。

For testing a System-on-Chip (SOC), it’s necessary to consider Design-For-Testability (DFT) by core providers. We propose an algorithm based on a framework of reconfigurable multiple scan chains for system-on-chip to minimize test application time. For the framework, the control signal combination causes the computing time increasing exponentially. The algorithm we proposed introduces a heuristic control signal selecting method to solve this problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan chains. It could show significant reductions in test application times and computing times.

Table of Contents
Chapter 1: Introduction……………………………………………………………1

1.1 Core-based Design ………………………………………………1
1.1.1 The evolution of design flow………………………………2
1.2 Test challengers in Core-based SOC designs………………4
1.2.1 Core test access………………………………………………6
1.3 TAM architecture…………………………………………………7
1.3.1 Basic TAM architecture………………………………………8
1.3.1.1 Basic TAM architecture……………………………………8
1.3.1.2 Scan-Chains…………………………………………………10
1.3.1.3 Test Wrappers architecture ……………………………11
1.3.2 Test Schedule…………………………………………………12
1.3.2.1 The Popular Rectangle Packing Model…………………12
1.3.2.2 The General Test Schedule………………………………15
1.3.2.2.1 The Serial Test Schedules……………………………16
1.3.2.2.2 The Parallel Test Schedules…………………………16
1.3.2.2.3 The Mixed test schedules ……………………………17
1.4 The outline of our method……………………………………18

Chapter 2 : Model of Reconfigurable Scan Chain ……………19

2.1 Example of Reconfigurable Multiple Scan Chains ………19
2.2 Variable definitions …………………………………………21
2.3 Test Sessions……………………………………………………22
2.4 Chain Cycles ……………………………………………………23
2.5 Control Signals…………………………………………………25
2.6 Test Clock Cycle Estimation…………………………………26

Chapter 3 : Control Signal Selection …………………………28

3.1 Constraints for the number of control signals…………28
3.2 Algorithm of Control Signal Selection……………………29
3.2.1 Control Signal Selected Table……………………………29
3.2.2 Algorithm of Control Signal Selection…………………29
3.3 The parameter p for increasing accuracy…………………33

Chapter 4 : Registers Assignment ………………………………34

4.1 The order for Registers Assignment ………………………34
4.1.1 The order of registers in a scan-chain ………………34
4.1.2 The order of test sessions for Registers Assignment36
4.2 The Blocks ………………………………………………………37
4.2.1 The Definitions of Blocks…………………………………37
4.2.2 The Cores of a single Block………………………………38
4.3 Algorithm of Registers Assignment…………………………42

Chapter 5 : Experimental Results ………………………………44

Chapter 6 : Conclusions……………………………………………49

References ……………………………………………………………50

List of Figures
Chapter 1
Figure 1.1 An example of SOC  ……………………………………2
Figure 1.2 A simplified chip design flow and industry relationships …………………………………………………………3
Figure 1.3 System design flow using core cells………………4
Figure 1.4 Overview of the test access in an embedded-core test………………………………………………………………………6
Figure 1.5, The test access architecture overview …………7
Figure 1.6 Multiplexing Architecture(a), Daisychain Architecture (b), and Distribution Architecture (c)………10
Figure 1.7 An overview of scan chain …………………………11
Figure 1.8 Core test wrapper ……………………………………12
Figure 1.9, TAM design using TAM width partition …………13
Figure 1.10, The test schedule of Figure 1.9 ………………13
Figure 1.11, The example rectangles for Core 6 in SOC p93791 …………………………………………………………………14
Figure 1.12, TAM design using generalized rectangle packing…………………………………………………………………14
Figure 1.13, The test schedule of Figure 1.12………………15
Figure 1.14, an example of the serial test schedules ……16
Figure 1.15, An example of the parallel test schedules …17
Figure 1.16, An example of the mixed test schedules………17
Figure 1.17, The basic flow………………………………………18

Chapter 2
Figure 2.1, an example of reconfigurable multiple scan chain design …………………………………………………………20
Figure 2.2, an example of Test sessions………………………22
Figure 2.3, Scan Chains for test session 1 of the example SOC………………………………………………………………………23
Figure 2.4, The registers bypassed by Ctrl1…………………24
Figure 2.5, Scan Chain for test session 2 of the example SOC………………………………………………………………………24

Chapter 3
Figure 3.1, The Algorithm of Control Signal Selection……29
Figure 3.2, the example of matrix M……………………………31
Figure 3.3, S1 and S2 on matrix M………………………………32
Figure 3.4, Updating matrix M……………………………………32
Figure 3.5, Next updating Matrix M ……………………………33

Chapter 4
Figure 4.1, The examples for the order of register in single scan-chain.(a) random ordered (b) specified ordered. ………………………………………………………………35
Figure 4.2, The advantage of the specified order …………36
Figure 4.3, the example of blocks………………………………37
Figure 4.4, The example of cores in blocks …………………39
Figure 4.5, The schedule after taking a choice ……………40
Figure 4.6, Algorithm of Registers Assignment………………42

List of Tables
Table 5.1 Test data for the core in SOC d695 ………………44
Table 5.2 Test data for the cores in SOC p93791……………45
Table 5.3, The comparison table 1………………………………47
Table 5.4, The comparison table 2………………………………48

[1] International SEMATECH. The International Technology Roadmap for Semiconductors (ITRS): 2001 Edition. http://public.itrs.net/Files/2001ITRS/Home.htm, 2001. 
[2] R.K. Gupta, Y. Zorian, “Introducing Core-Based System Design,” In Proceedings IEEE Design & Test of Computers, Volume: 14, Issue: 4, pp. 15 - 25, Oct.-Dec. 1997. 
[3] M. Keating and P. Bricaud. Reuse Methodology Manual For System-on-Chip Designs. Kluwer Academic Publishers, 1998. 
[4] IEEE P1500 Web Site, http://grouper.ieee.org/groups/1500/.
[5] Y. Zorian, E.J. Marinissen, and S. Dey, “Test Requirements for Embedded Core- Based Systems and IEEE P1500,” In Proceedings IEEE International Test Conference. (ITC), pp. 191-199, Nov. 1997.
[6]Yervant Zorian, Erik J. Marinissen, and Sujit Dey, “Testing Embedded-Core Based System Chips”, In proceedings IEEE International Test Conference, pp 130-134, 1998.
[7] J. Aerts and E.J. Marinissen, “Scan Chain Design for Test Time Reduction in Core-Based ICs,” In Proceedings IEEE International Test Conference (ITC), pp. 448-457, Washington, DC, Oct. 1998.
[8] Venkata Immaneni and Srinivas Raman. “Direct Access Test Scheme-Design of Block and Core Cells for Embedded ASICS,” In Proceedings IEEE International Test Conference (ITC), pp. 488-492, Sep. 1990.
[9] IEEE P1500 Web Site, http://grouper.ieee.org/groups/1500/.
[10] Yervant Zorian. “A Distributed BIST Control Scheme for Complex VLSI Devices,” In Proceedings IEEE VLSI Test Symposium, pp. 6-11, April 1993.

[11] E.J. Marinissen et al, “A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores,” In Proceedings IEEE International Test Conference (ITC), pp. 284-293, Washington, DC, Oct. 1998.
[12] V. Iyengar, K. Chakrabarty et al. “On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization,” In Proceedings IEEE VLSI Test Symposium (VTS), 2002, pp. 253-258.
[13] V. Iyengar, K. Chakrabarty and E.J. Marinissen, “Test wrapper and test access mechanism co-optimization for system-on-chip,” Proceeding of J. Electronic Testing: Theory and Applications, vol. 18, pp.211-228, March 2002.
[14] Md. Saffat Quasem, and Sandeep Gupta, “Designing Reconfigurable Multiple Scan Chains for System-on-Chip”, Proceeding of the 22nd IEEE VLSI Test Symposium (VTS 2004).
[15] Erik J. Marinissen, Vikram Iyegnar, and Krishnendu Chakrabarty, “ITC2002 SOC benchmarking initiative”, http://www.extra.research.philips.com/itc02socbenchm.
[16] V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “Efficient Wrapper/TAM Co-Optimization for Large SOCs”, in Proc. Design, Automation and Test in Europe (DATE), Paris, 2002, pp. 491-498.
[17] S.K. Goel and E.J. Marinissen, “Cluster-based Test Architecture Design for System-on-Chip,” In Proceedings  IEEE VLSI Test Symposium (VTS), 2002, pp. 259-264.
[18] S.K. Goel and E.J. Marinissen, “A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips,” Journal of Electronic Testing: Theory and Applications, 2003, pp. 425-435.

[19] Vikram Iyegnar, Krishnendu Chakrabarty, and Erik Jan Marinissen, “Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip”, In Proceedings IEEE International Test Conference, pp 1023-1032, 2001.
[20] Vikram Iyegnar, Krishnendu Chakrabarty, and Erik Jan Marinissen, “Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip”, IEEE Transaction on Computers, 52(12), pp. 1619-1631, 2003.
[21] Chih-pin Su, and Cheng-wen Wu, “A Graph-Based Approach to Power-Constrained SOC Test Scheduling”, Journal of Electronic Testing: Theory and Application 20, 45-60, 2004.
[22] Rajesh Gupta, Rajiv Gupta, and Melvin A. Breuer, “The BALLAST Methodology for Structured Partial Scan Design”, Proceeding in IEEE Transactions on Computers, VOL. 39, NO. 4, APRIL 1990.
[23] Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, and Yahya Zaidan, “Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm”, Proceeding in International Test Conference ITC 2002.
[24] Qiang Xu, and Nicola Nicolici, “On Reducing Wrapper Boundary Register Cell in Modular SOC Testing”, Proceeding in International Test Conference ITC 2003.
[25] Valentin Muresan, and Xiaojun Wang, “Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints”, Proceeding in JOURNAL OF ELECTRONIC TESTING: Theory and Applications 20, 61-78, 2004.
[26] Erik Larsson, Hideo Fujiwara, and Zebo Peng, “Efficient Test Solutions for Core-Based Designs”, Proceeding in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, NO. 5, MAY 2004.
[27] Md. Saffat Quasem, and Sandeep Gupta, “Designing Multiple Scan Chains for System-on-chip”, Asian Test Symposium, pp. 424-427, 2003.