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系統識別號 U0002-2708200714545200
中文論文名稱 具奈米牛頓解析度之互補式金氧半力感測器之研究
英文論文名稱 Research of the CMOS Force Sensor with Nano Newton Resolution
校院名稱 淡江大學
系所名稱(中) 機械與機電工程學系碩士班
系所名稱(英) Department of Mechanical and Electro-Mechanical Engineering
學年度 95
學期 2
出版年 96
研究生中文姓名 廖威豪
研究生英文姓名 Wei-Hao Liao
學號 694340281
學位類別 碩士
語文別 中文
口試日期 2007-07-10
論文頁數 57頁
口試委員 指導教授-楊龍杰
委員-李其源
委員-施文彬
委員-康尚文
中文關鍵字 互補式金氧半導體  微機電系統  壓阻式  力感測器 
英文關鍵字 CMOS MEMS  piezoresistive  force sensor 
學科別分類 學科別應用科學機械工程
中文摘要 本研究利用國家晶片系統設計中心所提供之台積電TSMC 0.35um 2P4M標準積體電路代工,製作感測薄膜為100um×100um大小之壓阻式力感測器;以二氧化矽做為感測薄膜,多晶矽做為壓電阻,並配合有限元素分析軟體ANSYS改善構形並預估其輸出靈敏度。
以正面濕式蝕刻方式減少晶粒面積浪費,利用硫酸雙氧水將金屬層蝕刻移去,其後利用氫氧化鉀(KOH)移除殘留金屬,續以氫氧化四甲銨(TMAH)對矽基底材蝕刻出V型槽(V-groove),得到感測薄膜之微結構。最後以反應離子蝕刻(RIE)移除金屬接腳之保護層並可藉此減薄感測薄膜厚度。蝕刻完成後,以市售雙排引腳形式之封裝電路板做晶粒之封裝。
本研究成功製作出CMOS微型壓阻式力感測器,並有效改善後製程蝕刻時間製作薄膜微結構,具面積小、靈敏度高之特性。模擬預估之靈敏度約為 -6.12 ×10-3 ∼ -2.36 uV/V/nN。
英文摘要 This research proposes a novel concept to fabricate a piezoresistive micro force sensor with a sensing membrane size of 100um×100um by using standard integrated circuit foundry, TSMC 0.35um 2P4M process herein, is provided by CIC (Chip Implementation Center), Taiwan. In this research, we use silicon dioxide as a material of a membrane of the sensor, and polysilicon as a material of piezoresistor. We design the shape of sensors and estimate the output sensitivity of sensor according to the result simulated by finite element method analyze software, ANSYS.
In order to reduce the waste of wafer area, front-side wet etching technique is adopted. We use piranha to remove the metal layers, and then use KOH to remove the residual metal and use TMAH to etch V-grooves of the silicon substrate. We can release the sensing membrane structure successfully by using this process. At last, we use RIE to remove the passivation on pad, by this way the thickness of the sensing membrane can be reduced. After wet etching and dry etching process, we package the dies by dual in-line package print circuit board which is sold in mart.
In this work, the piezoresistive micro force sensor made by CMOS MEMS technique has been fabricated successfully, and it effectively shorten the total time of post process. The micro force sensor has the advantages of smaller size and high sensitivity. In the simulation, we provide 10uN force and get the sensitivity about -6.12 ×10-3 ~ -2.36 uV/V/nN.
論文目次 目錄
中文摘要........................................................................................................I
英文摘要......................................................................................................II
目錄.............................................................................................................III
圖目錄..........................................................................................................V
表目錄......................................................................................................VIII

第一章 緒論
1-1 研究動機..........................................................................1
1-2 研究目的..........................................................................2
1-3 文獻回顧..........................................................................2
1-4 章節提要..........................................................................6
第二章 COMS-MEMS技術
2-1 標準CMOS製程簡介....................................................7
2-2 CMOS-MEMS技術及CMOS後製程...........................9
2-3 CMOS-MEMS製程侷限................................................9
2-4 全客戶式IC設計...........................................................10
第三章 設計原理
3-1 力感測器之種類............................................................12
3-2 壓阻式力感測晶片之感測原理....................................13
3-3 構形設計........................................................................15
3-4 有限元素法分析............................................................17
3-5 力感測晶片佈局設計....................................................25
第四章 後製程及量測
4-1 後製程流程....................................................................32
4-2 力感測晶片之封裝與量測............................................38
第五章 結果與討論
5-1 力感測晶片之蝕刻結果與討論....................................41
5-2 力感測晶片之封裝結果與討論....................................47
第六章 結論與建議
6-1 結論................................................................................50
6-2 建議................................................................................50
參考文獻.....................................................................................................53
附錄.............................................................................................................57

圖目錄
圖1.1  具有微型懸臂梁與微鉸鏈之CMOS微夾鉗力感測器...............3
圖1.2  經微細加工後之高深寬比微探針力感測器...............................4
圖1.3  以微探針對細胞進行擠壓及拉伸實驗.......................................4
圖1.4  CMOS多電極陣列電路晶片.......................................................5
圖1.5 封裝上PDMS的CMOS多電極陣列晶片.................................5
圖2.1  CMOS元件佈局圖.......................................................................8
圖2.2  CMOS元件結構剖面示意圖.......................................................8
圖2.3 CMOS 0.35μm 2P4M剖面示意圖...............................................8
圖3.1  惠斯登電橋.................................................................................14
圖3.2  壓電阻受力圖.............................................................................15
圖3.3  X狀和L狀感測薄膜構形.........................................................15
圖3.4  結構不對襯的X狀構形............................................................16
圖3.5  風車槳葉狀及三角探針狀感測薄膜構形.................................16
圖3.6  改良後之風車槳葉式薄膜.........................................................17
圖3.7  三角探針式薄膜之兩種不同角度設計.....................................17
圖3.8  定義材料特性.............................................................................18
圖3.9  整體幾何外貌.............................................................................19
圖3.10 薄膜結構之實體模型.................................................................19
圖3.11 薄膜結構之網格分割.................................................................19
圖3.12 風車槳葉薄膜構型施加均勻負載及集中負載.........................20
圖3.13 三角探針薄膜構型施加均勻負載及集中負載.........................20
圖3.14 風車槳葉薄膜構型施加負載後應力集中趨勢.........................21
圖3.15 三角探針薄膜構型施加負載後應力集中趨勢.........................21
圖3.16 矽的電阻率與摻雜濃度之關係.................................................22
圖3.17  n-type多晶矽摻雜濃度和規因數之關係................................23
圖3.18 各感測器構形.............................................................................23
圖3.19 製程堆疊示意圖.........................................................................26
圖3.20 Cadence軟體操作介面..............................................................27
圖3.21 壓電阻與懸橋外緣之距離示意圖.............................................28
圖3.22 多晶矽壓電阻與懸橋外緣之實際距離.....................................28
圖3.23 壓電阻之構形設計.....................................................................29
圖3.24 壓電阻之新構形設計.................................................................29
圖3.25 六種感測薄膜構形之佈局設計.................................................30
圖3.26 串聯運算放大器示意圖.............................................................31
圖3.27 可調配增益之運算放大器示意圖.............................................31
圖3.28 力感測晶片整體實際佈局圖.....................................................31
圖4.1  後製程實驗流程.........................................................................32
圖4.2  黏貼於蓋玻片及載玻片上之晶粒.............................................32
圖4.3  濕式蝕刻之實驗設備.................................................................33
圖4.4  研磨矽粉.....................................................................................35
圖4.5  以微量天平秤得適量矽粉.........................................................35
圖4.6  反應離子蝕刻機(RIE)..........................................................37
圖4.7  量測蝕刻速率之流程.................................................................38
圖4.8  實驗架構示意圖.........................................................................39
圖4.9  位於台灣大學應力所之原子力顯微鏡.....................................40
圖4.10 原子力顯微鏡探針.....................................................................40
圖5.1  未經後製程的晶粒.....................................................................41
圖5.2  濕蝕刻後製程完成後的晶粒.....................................................41
圖5.3  濕蝕刻後產生之倒金字塔形的V形槽......................................42
圖5.4  硫酸雙氧水蝕刻60分鐘後之表面深度....................................42
圖5.5  以KOH蝕刻120分鐘後,晶粒受損情形...................................44
圖5.6  以KOH蝕刻30分鐘後,晶粒外觀.............................................44
圖5.7  放大觀察KOH蝕刻30分鐘後之狀況.......................................45
圖5.8  放大觀察TMAH蝕刻90分鐘後之狀況....................................45
圖5.9 CF4蝕刻20分鐘後,晶粒之外觀................................................46
圖5.10 以SEM觀察CF4蝕刻20分鐘後,感測器之外觀......................46
圖5.11 電路板上之斷線.........................................................................47
圖5.12 雙排引腳形式的封裝電路板.....................................................48
圖5.13 穩壓電路之電路設計圖.............................................................48
圖5.14 實際電路板之設計.....................................................................49
圖5.15 48 pin IC腳座..............................................................................49
圖5.16 打線封裝完成,焊接於電路板上之力感測器...........................49
圖6.1  倒立式氣密CCD攝影模組........................................................51
圖6.2  細胞培養箱.................................................................................51

表目錄
表3.1 各感測器之模擬輸出結果...........................................................25
表4.1 濕蝕刻之金屬蝕刻液比例...........................................................33
表4.2 不同溫度之TMAH對矽之蝕刻速率.........................................36
表4.3 CF4氣體對各材料之蝕刻速率....................................................38
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