基於現今電子器材要求降低功率消耗的概念下，本論文提出了以降低輸入電壓為首要工作之低壓降線性穩壓器。在90nm製程下，輸入電壓為1V為基本，如何降低到0.5V以下系統人然能夠正常運作便是研究中的一個重要議題。低壓降線性穩壓器運用於提供穩定電壓，穩壓器是否能精確地輸出電壓為極重要的，因此，要判斷出穩壓器的可靠度及準確度，線性調節率與負載調節率變為重要的參數。
    本論文提出的電路可分為三部分，第一部分為粗調控制，利用漸進式移位暫存控制器的二分法概念產生出數位訊號控制功率電晶體以達到快速地輸出電壓，第二部分則為細調控制，以移位暫存器來細微調整輸出電壓的大小，使輸出電壓可以及靠近目標電壓，以求精準度，第三部分為比較器，此電路直接影響著整體電路事整體電路的精確度。由於功率電晶體會隨著製程及溫度偏異而改變，功率電晶體的大小便為重要，在此利用11 bit的移位暫存控制器來驅使足夠大的電晶體以求達到理想的輸出電壓，由於此時輸出電壓還未達到目標電壓，未達到相當精確，因此加入80級的移位暫存器來控制尺寸極小的功率電晶體，此微調範圍可包含於TT、FF、SS三種製程以及0°C、25°C及75°C三種溫度，使得規格都有符合預期之規格。
    上述的電路設計加以模擬驗證後可得到一輸入電壓低於0.5V之數位式超低壓低壓降線性穩壓器，輸入電壓為0.5V，輸出電壓為0.3V。最大負載電流為5mA，與精準度有關的負載調節率可達到0.516mV/mA，線性調節率達到6.88 mV/V，而靜態電流卻僅為26uA。

In this paper, the concept based on low power consumption, and reducing the input voltage is become the top priority. In 90nm process, the input voltage of 1V to basic, how to reduce to less 0.5V is an important topic in the study of normal operation. Low dropout regulator should be applied to provide a stable voltage, and the accuracy of output voltage is extremely important. So the line regulation and the load regulation will be the accuracy of the reference indicators.
    Therefore, the overall circuit can be divided into three parts. The first part is using SAR_Control digital signal to turn on the power transistor for achieving the output voltage. The second part is using shift register to fine tuning output voltage in order to accuracy. The third part is comparator. The size of power transistor will be important because the limit of the load current. Using 11 bit SAR_Control to drive transistor large enough for achieving the desired output voltage. The output voltage only close to the desired voltage, and it does not meet the extremely accurate. So adding 80 bit shift register to control the small size power transistor. The fine tuning range can be included in the TT, FF, SS, three kind of process, and can be meet the expected specifications.
    Though the above mentioned circuit design and simulation can be obtained a low input voltage Digitally Controlled LDO. The input voltage is 0.5V, and output voltage is 0.3V. When the heavy load current is 5mA, the line regulation is 0.516mV / mA, the load regulation is 6.88mV/V and the quiescent is only 26uA.

目錄
第一章  緒論	1
1.1 研究背景與動機	1
1.2 設計流程	2
1.3 論文架構	4

第二章  低壓降線性穩壓器	5
2.1低壓降線性穩壓器概論	5
2.2低壓降線性穩壓器之特性參數	7
2.2.1輸出電壓差	7
2.2.2靜態電流	8
2.2.3線性調節率	9
2.2.4負載調節率	10
2.2.5電源效率	12
2.2.6輸出準確率	12

2.3穩定性分析	15
2.3.1暫態響應	18
2.3.2頻率響應	21
2.4文獻分析	24
2.4.1具適應式偏壓網絡之LDO穩壓電路	24
2.4.2具有輔助推拉輸出級之低功耗快速鎖定低壓降穩壓電路	25
2.4.3具高效率低靜態電流之數位式低壓降線性穩壓器	26
2.4.4具有PLL調整、快速DVS電源管理之數位式低壓降線性器	27
2.4.5應用壓控時間延遲電路與相位比較器之數位控制LDO穩壓電路	28
2.4.6強化抑制電源雜訊能力之數位式LDO穩壓電路	29
第三章  超低壓降線性穩壓器設計	32
3.1低壓降線性穩壓器設計	32
3.1.1漸進式移位暫存控制器	34
3.1.2快速串列輸入、並列輸出的移位暫存器	36
3.1.3比較器	38
3.1.4 PMOS電源陣列	39
3.1.5 重新鎖定機制	40
3.2電路模擬與佈局	41
第四章  量測考量與結果分析	59
4.1量測考量	59
4.2量測結果與分析	60
第五章  結論	67
5.1結論與未來展望	67
參考文獻	68

圖目錄
圖1.1晶片設計流程圖	3
圖2.1傳統低壓降線性穩壓器之電路圖	6
圖2.2低壓降線性穩壓器之輸出/入電壓曲線圖	8
圖2.3靜態電流示意圖	9
圖2.4低壓降線性穩壓器之線性調節率示意圖	10
圖2.5低壓降線性穩壓器負載調節率示意圖	11
圖2.6輸出電壓誤差示意圖	12
圖2.7誤差放大器偏移示意圖	14
圖2.8電阻值誤差示意圖	14
圖2.9 PMOS功率電晶體的低壓降線性穩壓器	16
圖2.10 NMOS功率電晶體的低壓降線性穩壓器	16
圖2.11應用於SoC內的補償方式	17
圖2.12利用DFC電路調整相位邊限	18
圖2.13低壓降線性穩壓器及其輸出電容與負載電流	19
圖2.14低壓降線性穩壓器輸出電壓對負載電流之反應圖	19
圖2.15低壓降線性穩壓器之交流分析等效模型	21
圖2.16等效串聯電阻過大與過小的情況	23
圖2.17輕、重載與ESR補償	23
圖2.18具適應式偏壓網絡之LDO穩壓電路	25
圖2.19具有輔助推拉輸出級之低功耗快速鎖定低壓降穩壓電路	26
圖2.20具高效率低靜態電流之數位式低壓降線性穩壓器	27
圖2.21具有PLL調整、快速DVS電源管理之架構圖	28
圖2.22應用壓控時間延遲電路與相位比較器之數位控制LDO穩壓電路	29
圖2.23強化抑制電源雜訊能力之數位式LDO穩壓電路	30

圖3.1低輸入電壓之數位式低壓降線性穩壓器	32
圖3.2操作流程圖	33
圖3.3漸進式移位暫存控制器電路圖	34
圖3.4第k個多輸入移位暫存器與真值表	35
圖3.5解碼器與多工器電路圖	35
圖3.6 3-bit二元搜尋演算法流程圖	36
圖3.7快速八十位元串列輸入、並列輸出快速移位暫存器	37
圖3.8雙向移位暫存器的操作原理	37
圖3.9不受製程及溫度偏異影響之反相器	38
圖3.10反相器的特性曲線	39
圖3.11重新鎖定判斷機制	40
圖3.12低輸入電壓之數位式低壓降線性穩壓器	41
圖3.13輸出電壓穩定圖_輕載	42
圖3.14輸出電壓穩定圖_重載	44
圖3.15線性調節率模擬圖_輕載	45
圖3.16線性調節率模擬圖_重載	47
圖3.17負載調節率模擬圖	48
圖3.18電路佈局圖	50
圖3.19電路佈局示意圖	50
圖3.20 post-layout simulation輸出電壓穩定圖_輕載	51
圖3.21 post-layout simulation輸出電壓穩定圖_重載	52
圖3.22 post-layout simulation線性調節率模擬圖_輕載	54
圖3.23 post-layout simulation線性調節率模擬圖_重載	55
圖3.24 post-layout simulation負載調節率模擬圖	57
圖4.1量測儀器示意圖	59
圖4.2 Bonding wire之模型	59
圖4.3晶片俯視圖	60
圖4.4輕載量測圖	61
圖4.5重載量測圖	62
圖4.6線性調節率量測圖(輕載)	63
圖4.7線性調節率量測圖(重載)	64
圖4.8負載調節率量測圖	65
圖4.9 PSR量測圖	66

表目錄
表1.1線性穩壓器與切換式穩壓器之特性	2
表2.1 NMOS與PMOS 功率電晶體低壓降線性穩壓器的比較	15
表2.2文獻比較表	32
表3.1預計規格表	43
表3.2 pre-layout simulation results	50
表3.3 pre-layout simulation與post-layout simulation比較結果	59
表4.1 數位式控制的LDO穩壓器文獻比較表	66

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