隨著半導體製程技術的演進，電源電壓不斷的降低，信號大小亦隨之降低，唯有降低雜訊與誤差能量，才能在先進製程技術中製作高解析之三角積分調變器，藉由對物理特性上的低頻閃爍雜訊與寬頻熱雜訊的分析、控制與消除，再配合非理想電路的分析與設計始可得到最佳解析度。
本文針對低功率、高解析之三角積分調變器，分別應用於低頻帶與寬頻帶系統做最佳化設計考量與驗證。利用虛擬隨機切流式穩定技術降低閃爍雜訊對低頻帶信號的影響，同時降低調變器的輸出直流偏移電壓，實現一應用於生理信號頻帶之低雜訊調變器。另外，利用雙重取樣技術與多級串接式調變器架構，配合可切換式運算放大器，完成可應用於軟體定義無線電前端接收器之功率最佳化多模式調變器。論文中提出兩種不同應用的三角積分調變器：
其一，應用於生理信號之低雜訊三角積分調變器。使用台灣積體電路公司0.35微米製程，實現在3伏特電源電壓與950微瓦功率消耗之下，可達到92分貝的動態範圍與－135分貝的最低雜訊能量頻譜密度。利用所提出的虛擬隨機切流式穩定技術得到比傳統切流式穩定技術低6分貝的輸出直流偏移電壓，與比相關式雙重取樣技術低1.6分貝之最低雜訊能量頻譜密度。
其二，應用於GSM/WCDMA/WiMAX系統之可切換式雙重取樣多級串接式三角積分調變器。使用台灣積體電路公司0.13微米製程，實現在1.2伏特電源電壓與4.2/11.3/20.2毫瓦功率消耗之下，可達到100/72/75分貝的動態範圍與96/68/71分貝的信號雜訊失真比。利用所提出之可切換式雙重取樣多級串接式調變器架構，實現可多模式切換與功率最佳化之三角積分調變器。

With the progressing semiconductor process, the signal reduces with the decreasing power supply. Therefore, the only way to implement the high-resolution SDM in the modern process is to reduce the noise power. For reaching the high-resolution, the physical noises of the flicker and thermal ones have to be analyzed, controlled, and cancelled. Meanwhile, to model the circuit nonidealities and noise phenomena into the system design process can optimize the system coefficients for reducing power dissipation.
In this dissertation, low power and high-resolution SDMs are verified with the optimizing system and circuit design for the low and high bandwidth applications. The proposed pseudorandom chopper stabilization technique reduces the flicker noise and the offset voltage for low noise bio-signal SDMs. On the other hand, with switchable operational amplifier, the double-sampled multi-stage noise shaped (MASH) SDM optimizes power dissipation for multi-mode software-defined ratio (SDR) front-end receiver. The proposed SDMs are descript briefly as follows:
The proposed low noise bio-signal SDM is implemented with TSMC 0.35-um process. Using the proposed technique, the modulator achieves 92 dB of dynamic range and −135 dB of noise floor while consuming 950 μW from a 3 V supply. Based on the experimental results, the pseudorandom chopper-stabilization technique has a DC offset voltage that is 6 dB lower than that of the chopper-stabilization technique, and retains a thermal noise floor that is 1.6 dB lower than that of the correlated double sampling technique.
The proposed switchable double-sampled fourth-order MASH SDM is implemented with TSMC 0.13-um process. Using the switchable operational amplifier technique and proposed architecture, the modulator achieves 100/72/75 dB of dynamic range and 96/68/71 dB of signal to noise and distortion ratio while consuming 4.2/11.3/20.2 mW from a 1.2 V supply. Based on the power-optimized strategy from the views of circuit and system, the proposed SDM is a low power multi-mode modulator for the future SDR front-end receiver.

Table of Contents

CHAPTER 1	Introduction.......................................1
1.1	Motivation……………………………………….1
1.2	Research Goals…………………………………..4
1.3	Organization……………………………………..5
CHAPTER 2	Fundamentals of Sigma-Delta Modulator..........................................7
2.1 	Quantization Error……………………………….8
2.1.1	Quantization Error with Oversampling……………..9
2.1.2	Quantization Error with Oversampling and Noise Shaping……………………………………………11
2.1.2.1	First-Order SDM………………………………………12
2.1.2.2	Second-Order SDM……………………………………13
2.1.2.3	High-order SDM………………………………………14
2.2 	System Architecture……………………………15
2.2.1	Single-Loop Architecture………………………….15
2.2.2	Interpolative Architecture…………………………16
2.2.3	Cascaded Architecture…………………………….17
2.2.4	Low-Distortion Architecture………………………19
2.3 	Summary……………………………………….21
CHAPTER 3	Analysis of Circuit Non-idealities and Physical Noises in Sigma Delta Modulator…………………………22
3.1	Top-Down Design……………………………...22
3.2	Systematic Design……………………………...24
3.2.1	Circuit Non-Idealities……………………………..24
3.2.2	Switches Thermal Noise…………………………..25
3.2.3	Finite Gain of Operational Amplifier……………..28
3.2.4	Finite Unity Gain Bandwidth and Finite Slew Rate……………………………………..……….31
3.2.4.1	Integrating Phase………………………………………31
3.2.4.2	Sampling Phase………………………………………..35
3.2.5	Uncertain Sampling Time…………………………35
3.3	Noise Sources and Cancellation Techniques…...37
3.3.1	Noise Sources……………………………………..37
3.3.2	Offset Voltage……………………………………..39
3.3.3	CDS Technique……………………………………39
3.3.4	CHS Technique……………………………………40
3.4 Summary………………………………………..…43
CHAPTER 4	A Low-Offset Low-Noise Sigma-Delta Modulator with Pseudorandom Chopper-Stabilization Technique…………………………44
4.1	Introduction…………………………………….44
4.2	Pseudorandom CHS Technique………………...45
4.2.1	Impact of the Offset Voltage………………………45
4.2.2	Behavioral Model of the Proposed Technique…….47
4.2.3	Pseudorandom Sequence Generator………………49
4.2.4	Design Principle…………………………………..50
4.3	Design of System and Circuit………………….51
4.3.1	System Design…………………………………….51
4.3.2	Circuits Design……………………………………53
4.3.3	Decimation Filter………………………………….55
4.4	Measurement Results…………………………..56
4.5	Summary…………………………………….…65
CHAPTER 5	Low Power Design Strategy of Reconfigurable Multi-Mode Double-Sampled MASH SDM for GSM/WCDMA/WiMAX Applications………………………67
5.1	Introduction………………………………….....67
5.2	System Considerations…………………………70
5.2.1	Double-Sampled Technique………………….……71
5.2.1.1	Preliminary……………………………………...……..71
5.2.1.2	Mismatching Error………………………………….…72
5.2.2	Multi-Mode MASH SDM……………………..…..74
5.2.3	System Synthesis………………………………….78
5.2.4	Low Power Design Strategy………………………82
5.2.5	System Simulation……………………………...…84
5.3	Circuit Design………………………….………88
5.3.1	Architecture of Opamp…………………...……….89
5.3.2	Quantizer…………………………………………..94
5.3.3	Clock Generator……………………………...……94
5.3.4	Circuit of Each Stage…………………………...…97
5.3.5	Circuit Simulation Results…………………….…102
5.4	Measurement Results…………………………105
5.5	Summary…………………………………...…113
CHAPTER6	Conclusion and Future Work….…114
6.1	Conclusion………………………………….....114
6.2	Future work………………………………..….115
APPENDIX A………………………………………116
APPENDIX B………………………………………118
REFERENCES………………………………………119
LIST OF FIGURES

Fig. 1.1		Application range with the resolution-speed plan………………………………..2
Fig. 2.1	Model of quantizer: (a) Ideal transfer curve, (b) Ideal error curve, (c) Linear model, (d) Signal-independent white noise, (e) First order linear model………..8
Fig. 2.2 	Effect of the oversampling……………………………………………………...10
Fig. 2.3		Linear model of a general noise-shaping SDM…………………………...…….11
Fig. 2.4		Effect of the noise shaping…………………………………………………...…12
Fig. 2.5		The traditional first-order SDM……………………………………...…………13
Fig. 2.6		The second order SDM………………………………………………………….13
Fig. 2.7		SNRmax vs. OSR…………………………………………………………….…..15
Fig. 2.8		Generalized high-order single-loop SDM……………………………...……….16
Fig. 2.9		High order interpolative modulator……………………………………………..17
Fig. 2.10	General case of MASH architecture………………………………………...…..18
Fig. 2.11 (a) Traditional topology, (b) Low-distortion topology…………………………..20
Fig. 2.12 (a) PSD of the traditional topology; (b) Output swing of the first integrator of  the traditional topology; (c) Output swing of the second integrator of the traditional topology; (d) PSD of the low-distortion topology; (e) Output swing  of the first integrator of the low-distortion topology; (f) Output swing of the second integrator of the low-distortion topology……………………………….20
Fig. 2.13	General topology of a low-distortion single-loop SDM…………………….…..21
Fig. 3.1 	Design flow……………………………………………………………..………23
Fig. 3.2 	Non-ideal system model…………………………………………..…………….25
Fig. 3.3 	(a) SC integrator, (b) sampling mode, and (c) evaluation mode………………..27
Fig. 3.4 	SNRkT/C vs. Vref……………………………………………….………………….28
Fig. 3.5 	Behavior models of (a) ideal integrator, (b) leaky integrator……………...……28
Fig. 3.6 	MASH 1-1 SDM with non-ideal integrator………………………………….….31
Fig. 3.7 	Evolution of evaluation phase…………………………………………….…….32
Fig. 3.8 	Dependence of sampling instant on input level…………………………………36
Fig. 3.9 	SDR vs. uncertain sampling time…………………………………………...…..37
Fig. 3.10	Noise model……………………………………………………………………..38
Fig. 3.11	Input-referred offset voltage model……………………………………………..39
Fig. 3.12	Switched-capacitor integrator with correlated double sampling technique…….40
Fig. 3.13	Chopper-stabilization operational amplifier…………………………………….43
Fig. 4.1 	Matlab model of the offset voltage…………………………...…………………46
Fig. 4.2 	SNDR vs. DC gain and normalized offset voltage……………...………………47
Fig. 4.3 	Residual offsets caused by spikes of CHS and pseudorandom CHS…………...48
Fig. 4.4 	Sixth-order pseudorandom sequence generator…………………………….…..50
Fig. 4.5 	Third-order cascaded integrators with weighted feed-forward path SDM..........52
Fig. 4.6 	Root locus diagram……………………………………………………………...54
Fig. 4.7 	Fully differential folded-cascode amplifier with switched capacitor common mode feedback circuit…………………………………………………………..54
Fig. 4.8 	Whole circuit diagram of the system……………………………………..…..…55
Fig. 4.9 	The architecture of the decimator…………………………………….…………56
Fig. 4.10	Chip micrograph of the proposed SDM…………………………………...……57
Fig. 4.11	Printed circuit board…………………………………………………...………..58
Fig. 4.12	Pin configuration diagram………………………………………………………59
Fig. 4.13	The measurement environment…………………………………………………60
Fig. 4.14	Regulator with LM-317…………………………………...…………………….60
Fig. 4.15	Analog buffer with Op-27………………………………………………………61
Fig. 4.16	Measured dynamic ranges of the techniques of CDS, CHS and pseudorandom CHS with 1.024 MHz of the sampling frequency…………………………...…62
Fig. 4.17	Measured nonlinear harmonic increase…………………………………………63
Fig. 4.18	Measured power spectrums of the techniques of CDS, CHS and pseudorandom CHS with 1.024 MHz of the sampling frequency……………………………...63
Fig. 4.19	Measured harmonic distortions from signal source power……………………..64
Fig. 4.20	The 1,048,576-point power spectrum of the output of the proposed modulator and the 8,192-point power spectral density of the output of the decimator ……65
Fig. 5.1	Architecture of SDR transreceiver……..…………...…………………….…….68
Fig. 5.2		Conventional double-sampled integrator……………………………………….72
Fig. 5.3		Floating double sampling integrator………………………………...…………..73
Fig. 5.4	Model of the mismatching in the conventional double-sampled integrator…....73
Fig. 5.5	(a) the conventional non-delay double-sampled integrator, and (b) the conventional bilinear integrators. ……………………………………...………74
Fig. 5.6		Model of the conventional double-sampled bilinear integrator………………...74
Fig. 5.7 	The proposed MASH SDM…………………………………………..…………76
Fig. 5.8 	Root locus plot of the proposed SDM for the proposed systems……………….78
Fig. 5.9 	The synthesized frequency response of the proposed modulator………….……79
Fig. 5.10	The SNDR surface vs. Qmax and k………………………………………………80
Fig. 5.11	Power-optimization strategy………………………………………………...…..83
Fig. 5.12	SNDR surface with varying Av and acc in the primary integrator…………..…..84
Fig. 5.13	SNDR surface with varying Av and acc in the second integrator of the first stage……………………………………………………………………...……..85
Fig. 5.14	SNDR surface with varying Av and acc in the integrators and summer of the second stage……………………………………………………………….……85
Fig. 5.15	SNDR vs. Cs and double-sampled mismatch ratio in the first stage…………….86
Fig. 5.16	SNDR vs. Cs and double-sampled mismatch ratio in the second stage………....87
Fig. 5.17	The diagram of power spectrum density of the WiMAX mode…………….…..87
Fig. 5.18	The diagram of dynamic ranges on the proposed modulator for different modes………………………………………………………………………..….88
Fig. 5.19	Gain boosting telescopic opamp for the primary integrator……………..……...91
Fig. 5.20	Telescopic opamp for the second integrator and summer in the first stage….…92
Fig. 5.21	Telescopic opamp for the second stage…………………………………………92
Fig. 5.22	The double-sampled common mode feedback (CMFB) circuit…………...……93
Fig. 5.23	The bias circuit………………………………………………………...………..93
Fig. 5.24	The 3-level quantizer……………………………………………………...…….95
Fig. 5.25	The timing diagram of each phase of sampling clock……………………….….95
Fig. 5.26	The circuit blocks of the clock generator……………………………………….96
Fig. 5.27	The parasitic model of the bonding pad…………………………...……………97
Fig. 5.28	SC branch……………………………………………………………………….98
Fig. 5.29	The first integrator in each stage………………………………………….…….99
Fig. 5.30	The second integrator in each stage……………………………...……………100
Fig. 5.31	The summer in each stage……………………………………………………..101
Fig. 5.32	The encoder in each stage……………………………………………………..102
Fig. 5.33	The PSD of each mode by the post-layout simulation…………………..…….104
Fig. 5.34	The chip micrograph…………………………………………………………..106
Fig. 5.36	The pin configuration diagram……………………………..………………….106
Fig. 5.35	The measurement environment………………………………………………..107
Fig. 5.37	Differential input filter…………………………………………………..…….108
Fig. 5.38	PCB photograph……………………………………………………………….108
Fig. 5.39	The measured power spectrums for the GSM mode (a) without input signal,   (b) with input signal……………………………………………………….......110
Fig. 5.40	The measured power spectrums for the WCDMA mode (a) without input  signal, (b) with input signal……………………………………………...…….111
Fig. 5.41	The measured power spectrums for the WiMAX mode (a) without input   signal, (b) with input signal………………………………………………...…112
Fig. A1	(a) Single-end SC integrator, (b) Equivalent circuit at the evaluating phase  with offset voltage……………………………………………………….……117













LIST OF TABLES

Table 1.1		Life-time of three types of cells with ADC has power dissipation of 100mW……………………………………………………………………...3
Table 1.2		Bio-signal bandwidths………………………………………………………4
Table 1.3		Next generation communication system specifications…………………….5
Table 4.1		Specifications of the decimator……………………………………..……..56
Table 4.2		Measurements of the experimental prototypes……………………….……58
Table 4.3		Performance comparisons……………………………………...………….61
Table 4.4		Calculated offset voltages after decimation……………………...………..65
Table 5.1		Coefficients of the proposed SDM…………………………………...……79
Table 5.2		SNDR vs. Qmax and k………………………………………………………80
Table 5.3		Output swing at each integrator…………………………………...……….81
Table 5.4		Maximum output amplitude of each integrator with gsi = 4……………….81
Table 5.5		The dynamics range of the proposed SDM by Matlab simulation………...88
Table 5.6		Operation modes vs. switching status……………………..………………90
Table 5.7		Specifications of the opamp…………………………………...…………..90
Table 5.8		Switch size list vs. different sampling capacitors………………………….98
Table 5.9		Performance summary of each application………………………………103
Table 5.10	Specifications of each opamp…………………………………………….103
Table 5.11	Corner simulation results for the WiMAX mode……………….………..104
Table 5.12	Comparison………………………………………………………………105

References
[1]	R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, IEEE press, Wiley Interscience, 2005.
[2]	T. Christen, T. Burger, and Q. Huang, “A 0.13μm CMOS EDGE/UMTS/WLAN tri-mode ΔΣ ADC with -92dB THD,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2007, pp. 240-242.
[3]	K. Vleugels, S. Rabii, and B. A. Wooley, “A 2.5-V sigma-delta modulator for broadband communications applications,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1887-1899, Dec. 2001.
[4]	R. Bagheri, A. Mirzaei, M. E. Heidari, S. Chehrazi, M. Lee, M. Mikhemar, W. K. Tang, and A. A. Abidi, “Software-Defined Radio Receiver: Dream to Reality,” IEEE Comm. Magazine, pp. 111-118, Aug. 2006.
[5]	A. Baschirotto, F. Campi, R. Castello, G. Cesura, R. Guerrier, L. Lavagno, A. Lodi, P. Malcovati, and M. Toma, “Baseband Analog Front-End and Digital Front-End for Reconfigurable Multi-Standard Terminals,” IEEE Circuits and Systems Magazine, vol. 1, pp. 8-28, 2006.
[6]	X. Li, W. Wu, G. Gildenblat, G.D.J. Smit, A.J. Scholten, D.B.M. Klaassen, and R. van Langevelde, Technical Note NXP-R-TN-2008/00299, NXP Semiconductors, 2008.
[7]	P. G. Drennan, M. L. Kniffin, and D. R. Locascio, “Implications of Proximity Effects for Analog Design,” IEEE Custom Intergrated Circuits Conference, Sept. 2007, pp. 169-176.
[8]	B. Razavi, Design of Analog CMOS Integrated Circuits, McGRAW-HILL, 2001.
[9]	K. C. H. Chao, S. Nadeem, W. L. Lee and C. G. Sodini, “A higher order topology for interpolative modulators for oversampling A/D conversion,” IEEE Trans. on Circuits and Systems, vol. 37, pp. 309-318, Mar. 1990.
[10]	T. Hayashi, Y. Inabe, K. Uchmura, and T. Kimura, “A Multistage Delta-Sigma Modulator without Double Integration Loop,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 1986, pp.182-183.
[11]	S. M. C. Willy, Q. Huang, and H. I. Kari, “Transient Analysis of Charge Transfer in SC Filters － Gain Error and Distortion,” IEEE J. Solid-State Circuits, vol. 22, no. 2, pp. 268-276, Apr. 1987.
[12]	J. Silvia, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-distortion delta-sigma ADC topology,” IET Electronic Letters, vol. 37, no. 12, pp. 737-738, Jun. 2001.
[13]	U. Chilakapati and T. S. Fiez, “Effect of Switch Resistance on the SC Integrator Settling Time,” IEEE Trans. On Circuits and Systems II, vol. 46, no. 6, pp. 810-816, Jun. 1999.
[14]	B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995.
[15]	C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of opamp imperfactions: Autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, pp. 1584-1614, Nov. 1996.
[16]	R. Schreier, J. Silvia, J. Steensgaard, and G. C. Temes, “Design-Oriented Estimation of Thermal Noise in Switched-Capacitor Circuits,” IEEE Trans. on Circuits and Systems I, vol. 52, no. 11, pp. 2358-2368, Nov. 2005.
[17]	D. A. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.
[18]	M. H. White, D. R. Lampe, F. C. Blaha, and I. A. Mack, “Characterization of surface channel CCD image arrays at low light levels,” IEEE J. Solid-State Circuits, vol. 9, no. 1, pp. 1-13, Feb. 1974.
[19]	J. Williams, “Application consideration and circuits for a new chopper-stabilized Op Amp,” Linear Technology online publications, March 1985.
[20]	L. Tóth and Y. P. Tsividis, “Generalization of the Principle of Chopper Stabilization,” IEEE Trans. on Circuits and Systems I, vol. 50, no. 8, pp. 975-983, Aug. 2003.
[21]	A. Agnes, A. Cabrini, F. Maloberti, and G. Martini, “Cancellation of Amplifier Offset and 1/f Noise: An Improved Chopper Stabilized Technique,” IEEE Trans. on Circuits and Systems II, vol. 54, no. 6, pp. 469-473, Jun. 2007.
[22]	A. Bakker, K. Thiele, and J. H. Huijsing, “A CMOS nested-chopper instrumentation amplifier with 100-nV offset,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1877-1883, Dec. 2000.
[23]	P. Malcovati, S. Brigati, F. Francesconi, F. Medeiro, P. Cusinato, and A. Baschirotto, “Behavioral Modeling of Switched-Capacitor Sigma-Delta Modulator,” IEEE Trans. on Circuits and Systems I, vol. 50, no. 3, pp. 352-364, Mar. 2003.
[24]	G. Suárez, M. Jiménez, and F. O. Fernéndez, “Behavioral Modeling Methods for Switched-Capacitor ΣΔ Modulators,” IEEE Trans. on Circuits and Systems I, vol. 54, no. 6, pp. 1236-1244, Jun. 2007.
[25]	J. Candy, “Decimation for Sigma-Delta Modulation,” IEEE Trans. on Communications, vol. 34, pp. 72-76, Jan. 1986.
[26]	M. Laddomada, “Generalized Comb Decimation Filters for ΣΔ A/D Converters: Analysis and Design,” IEEE Trans. on Circuits and Systems I, vol. 54, no. 5, pp. 994-1005, May 2007.
[27]	M. Laddomada, “On the Polyphase Decomposition for Design of Generalized Comb Decimation filters,” IEEE Trans. on Circuits and Systems I, vol. 55, no. 8, pp. 2287-2299, Sep. 2008.
[28]	K. Ishida and M. Fujishima, “Chopper-stabilized high-pass sigma delta modulator utilizing a resonator structure,” IEEE Trans. on Circuits and Systems II, vol. 50, no. 9, pp. 627-631, Sept. 2003.
[29]	Y. H. Chang, C. Y. Wu, and T. C. Yu, “Chopper-stabilized sigma delta modulator,” in IEEE Int. Symp. on Circuits and Systems (ISCAS), May 1993, pp. 1286-1289.
[30]	M. Dessouky and A. Kaiser, “Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 349-355, Mar. 2001.
[31]	J. Sauerbrey, T. Tille, D. Schmitt-Landsiedel, and R. Thewes, “A 0.7-V MOSFET-only switched-opamp ΣΔ modulator in standard digital CMOS technology,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1662-1669, Dec. 2002.
[32]	L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-μW 88-dB audio sigma-delta modulator in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1809-1818, Nov. 2004.
[33]	G.-C. Ahn, D.-Y. Chang, M. E. Brown, N. Ozaki, H. Youra, K. Yamamura, K. Hamashita, K. Takasuka, G. C. Temes, and U.-K. Moon, “A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2398-2407, Dec. 2005.
[34]	J. Roh, S. Byun, Y. Choi, H. Roh, Y.-G. Kim, and J.-K. Kwon, “A 0.9-V 60μW 1-bit fourth-order delta-sigma modulator with 83-dB dynamic range,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 361-370, Feb. 2008.
[35]	G. Gomez and B. Haroun, “A 1.5V 2.4/2.9mW 79/50dB ΣΔ Modulator for GSM/WCDMA in a 0.13um Digital Process,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2002, pp. 242-490.
[36]	A. Dezzani and E. Andre, “A 1.2-V Dual-Mode WCDMA/GPRS ΣΔ Modulator,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2003, pp. 58-59.
[37]	J. Yu and F. Maloberti, “A Low-Power Multi-Bit ΔΣ Modulator in 90nm Digital CMOS without DEM,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2005, pp. 168-591.
[38]	A. Rusu, D. R. L. González, and M. Ismail, “Reconfigurable ADCs Enable Smart Radios for 4G Wireless Connectivity,” IEEE Circuits & Devices Magazine, pp. 6-11, May/June 2006.
[39]	T. Christen, T. Burger, and Q. Huang, “A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THD,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2007, pp. 240-599.
[40]	Y. Ke, J. Craninckx, andG. Gielen, “A Design Approach for Power-Optimized Fully Reconfigurable ΔΣ A/D Converter for 4G Radios,” IEEE Trans. on Circuits and Systems I, vol. 55, no. 3, pp. 229-233, Mar. 2008.
[41]	P. Balmelli and Q.Huang, “A 25 MS/s 14b 200mW Sigma Delta Modulator in 0.18um CMOS,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2004, pp. 74-514.
[42]	P. J. Hurst and W. J. McIntyre, “Double Sampling in Switched-Capacitor Delta-Sigma A/D Converters,” in IEEE Int. Symp. on Circuits and Systems (ISCAS), May 1990, pp. 902-905.
[43]	T.V. Burmas, K.C. Dyer, P.J. Hurst, and S.H. Lewis, “A Second-Order Double-Sampled Delta-Sigma Modulator using Additive-Error Switching,” IEEE J. Solid-State Circuits, vol. 31,  no. 3,  pp. 284-293, March 1996.
[44]	C.K. Thanh, S.H. Lewis, P.J. Hurst, “A Second-Order Double-Sampled Delta-Sigma Modulator using Individual-Level Averaging,” IEEE J. Solid-State Circuits, vol. 32,  no. 8,  pp. 1269-1273, Aug. 1997.
[45]	D.Senderowicz, G. Nicollini, S. Pernici, A. Nagari, P. Confalonieri, and C. Dallavalle, “Low-Voltage Double-Sampled ΣΔ Converters,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1907-1919, Dec. 1997.
[46]	K. Vleugels, S. Rabii, and B. A. Wooley, ”A 2.5-V Sigma-Delta Modulator for Broadband Communication Applications,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1887-1899, Dec. 2001.
[47]	M. G. Kim, G.C. Ahn, P.K. Hanumolu, S.H. Lee, S.H. Kim, S.B. You, J.W. Kim, G.C. Temes, and U.K. Moon, “A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC,” IEEE J. Solid-State Circuits, vol. 43,  no. 5, p.p. 1195-1206, May 2008.
[48]	P. Rombouts, J.D. Maeyer, and L. Weyten, “Design of Double-Sampling ΣΔ Modulation A/D Convertors With Bilinear Integrators,” IEEE Trans. on Circuits and Systems I, vol. 52, No. 4, pp. 715-722, Apr. 2005.
[49]	T. Yamamoto, M. Kasahara, and T. Matsuura, “A 63-mA 112/94-dB DR IF Bandpass ΔΣ Modulator with Direct Feed-forward and Double Sampling,” in IEEE Custom Intergrated Circuits Conf. (CICC), Sept. 2007, pp.61 – 64.
[50]	R. Schreier, Delta SigmaToolbox, Matlab Central, 11 Feb. 2008.
[51]	O. Choksi and L. R. Carley, “Analysis of Switched-Capacitor Common-Mode Feedback Circuit,” IEEE Trans. on Circuits and Systems II, vol. 50, no. 12, pp. 906-917, Dec. 2003.
[52]	S. Kwon, and F. Maloberti, “A 14mW Multi-bit ΔΣ Modulator with 82dB SNR and 86dB DR for ADSL2+,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2006, pp. 161-170. 
[53]	K.-S. Lee, S. Kwon, and F. Maloberti, “A 5.4mW 2-Channel Time-Interleaved Multi-bit ΔΣ Modulator with 80dB SNR and 85dB DR for ADSL,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2006, pp. 171-180. 
[54]	Y. Fujimoto, Y. Kanazawa, P. Lore, and M. Miyamoto, “An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Reciever,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2006, pp. 201-210. 
[55]	P. Malla, H. Lakdawala, K. Kornegay, and K. Soumyanat, “A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMAX Receivers,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2008, pp. 496-631.
[56]	K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuk, S. Takeuch, and G. C. Teme, “A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR,” in IEEE Int. Solid State Circuits Conf. (ISSCC), Feb. 2008, pp. 494-631.
[57]	H. C. Yang and D. J. Allstot, “Considerations for Fast Settling Operational Amplifiers,” IEEE Trans. on Circuits and Systems, vol. 37, no. 3, pp. 326-334, Mar. 1990.
[58]	K. D. Chen and T. H. Kuo, “An Improved Technique for Reducing Baseband Tones in Sigma-Delta Modulators Employing Data Weighted Averaging Algorithm Without Adding Dither,” IEEE Trans. on Circuits and Systems II, vol. 46, no. 1, pp. 63-68, Jan. 1999.
[59]	J. V. d. Spiegel and K. C. Smith, “Writing a Good ISSCC Paper,” in IEEE Int. Asian Solid State Circuits Conf. (ASSCC), Nov. 2006.
[60]	F. Medeiro, A. Pérez-Verdú and A. Rodríguez-Vázquez, Top-Down Design of High-Performance Sigma-Delta Modulators, Kluwer, 1999.