隨著科技產業持續不斷的進步，家庭及公司諸如此類的小區域使用的電子產品量亦隨之成長，有線產品造成環境維持不易的問題漸漸地浮現，為了解決這個問題，產品無線化已成為目前的趨勢，而短距離的無線通訊也成為不可缺少的技術之一。一般常見的低功率短距離無線通訊技術不外乎就是紅外線，而生活中最常見的紅外線應用就是遙控器，但它卻有許多不方便的缺點，譬如：傳輸距離短、方向性受限制、傳輸時其中間不能有任何東西阻擋，且同時只能有兩個裝置互相連結；所以，本論文提出一使用高斯頻率鍵移(Gaussian Frequency Shift Keying, GFSK)調變技術之傳收機，其不僅保有紅外線省電的優點，且傳輸距離較紅外線要更長，加上方向不受限制、同時可有兩個以上裝置互相連結的優異特性，使得產品的應用性以及便利性大大的增加。
本篇論文嘗試以Top-Down的概念設計一GFSK調變系統；我們使用硬體描述語言(Verilog HDL)撰寫一中頻為1MHz之GFSK調變系統，並將其燒錄於FPGA上實現所設計之系統電路。在傳送端我們使用一PN Sequence產生資料源，資料經過Scrambler、Manchester Encoder、Convolutional Encoder和Interleaver編碼後，在進入Modulation前將先經過一Gaussian Filter，此程序會將信號變的較為平滑，使信號在調變時不至於產生太大的帶外頻譜(Out-of-band Spectrum)，也因為GFSK的特性，使得信號比較不容易受到相鄰頻道信號的干擾。信號由GFSK Modulation調變後發送，經過加成性白色高斯雜訊(Additive White Gaussian Noise, AWGN)以及限幅放大器(Limiting Amplifier)，或是經過RF Module再傳送至接收端，接著由GFSK Demodulation、IIR Filter、Deinterleaver、Viterbi Decoder、Manchester Decoder和Descrambler方塊做解碼以及解調變後，量測系統之位元錯誤率 (Bit Error Rate, BER)以驗證所設計之硬體電路。

Along with the industry technology incessant progress, the demand for electronic products in the family and offices is extremely increased especially for the short range application products. However it appears that in the utilization of these wired electronic products it generates the problem of not easy to maintain a safe and clean environment. It is imperative and a trend that these wired electronic products will be replaced by their wireless counterparts and consequently it becomes indispensable that it needs to develop the technology for short range wireless transmission. The commonly used technology in the low power and short range transmission environment is the infrared system, and the most application of the infrared technology is the use of remote controller in the daily life. But it has many inherent shortcomings in the infrared technology, for example, its transmitting range is short, its transmission direction is confined, it needs to have a clear path in its transmission and it can have only two devices interconnected simultaneously. In this thesis we propose a transceiver system that is implemented by using the Gaussian Frequency Shift Keying method. It has the advantages that it has not only the merits of the infrared technology but it also has longer transmission range than that of the infrared system, it has no confining direction in its transmission and it can have more than two devices interconnected simultaneously. Because of the afore-mentioned advantages the wireless electronic products have become more pleasing and convenience to use and have been found more application areas. 
In this thesis we propose the design of a GFSK modulation system based on the Top-Down design concept. We use Verilog hardware description (HDL) language to design a GFSK modulation system with intermediate frequency set at 1 MHz. This designed system is implemented on the FPGA application platform. The information data is generated through the implementation of a pseudo noise generator, the data is passing through scrambler, manchester encoder, convolutional encoder, Interleaver  and passed through a Gaussian filter before they enter into the modulator. The Gaussian filter will smooth the data stream to avoid the possibility of generating out-of-band spectrum before it enters the modulator, and due to this spectrum smoothing characteristic it will reduce the interference effect from the neighboring channels. The modulated signal is then transmitted through the white noise affected channel and limiting amplifier or RF module to the receiver end. At the receiver the received signal is passing through the, demodulator, infinite impulse response (IIR) filter, deinterleaver, Viterbi decoder and the descrambler to regenerate the transmitted data. The system bit error rate (BER) is measured and analyzed. The system performance can be improved by implementing error correcting block in the system.

第一章	緒論 ……………………………………………………	1
	1.1  研究背景 ………………………………………	1
	1.2  研究動機與目的 ………………………………	1
	1.3  論文架構 ………………………………………	2
第二章	GFSK傳收機之系統設計 ………	……………………	3
	2.1  GFSK傳收機規格 ………………………………	3
	2.2  GFSK傳收機發送端設計 ………………………	6
		2.2.1  PN Sequence	……………………	6
		2.2.2  Manchester Encoder	…………	8
		2.2.3  Scrambler	………………………	10
		2.2.4  Interleaver	……………………	12
	2.3  GFSK傳收機接收端設計 ………………………	14
		2.3.1  CLK偵測	………………………	15
		2.3.2  前置碼偵測	……………………	17
		2.3.3  Demodulation ……………………	19
		2.3.4  Deinterleaver …………………	20
		2.3.5  Descrambler	 ……………………	22
		2.3.6  Manchester Decoder ……………	24
	2.4  AWGN ……………………………………………  26
第三章	錯誤更正碼設計 ……………………………………	28
	3.1  Convolutional Encoder	……………………	28
	3.2  Viterbi Decoder ……………………………	31
第四章	GFSK傳收機之實現與量測 ……	……………………	35
	4.1  FPGA設計流程	………………………………… 35
	4.2  實測結果 ……………………………………	36
		4.2.1  硬體實現耗費之LE及記憶體……	36
		4.2.2  BER量測	………………………	38
第五章	結論與未來展望	………………………………	46
	5.1  結論	……………………………………………	46
	5.2  未來展望	…………………………………	46
參考文獻	………………………………………………………	47

圖目錄
圖2.1	GFSK接收機系統方塊	………………………………	4
圖2.2	GFSK系統規格	…………………………………	4
圖2.3	不同Mode時各個方塊所需之CLK	…………………	5
圖2.4	CLK Tree	…………………………………………	5
圖2.5	PN9架構圖	…………………………………………	6
圖2.6	PN Sequence方塊圖	………………………………	7
圖2.7	PN Sequence動作時序圖	………………………	7
圖2.8	PN Sequence波形模擬圖	………………………	8
圖2.9	Manchester Encoder方塊圖	………………………	8
圖2.10	Manchester Encoder動作時序圖 ……………………	9
圖2.11	Manchester Encoder波形模擬圖 ……………………	9
圖2.12	Scrambler架構圖	…………………………………	10
圖2.13	Scrambler方塊圖	…………………………………	11
圖2.14	Scrambler動作時序圖 ………………………………	11
圖2.15	Scrambler波形模擬圖 ………………………………	12
圖2.16	Interleaver輸入/出說明 ……………………………	13
圖2.17	Interleaver方塊圖	…………………………………	13
圖2.18	Interleaver動作時序圖 ……………………………	14
圖2.19	Interleaver波形模擬圖 ……………………………	14
圖2.20	前置碼格式…………………………………………	15
圖2.21	CLK偵測程序………………………………………	16
圖2.22  	CLK偵測動作說明	…………………………………	17
圖2.23	前置碼偵測步驟1	…………………………………	18
圖2.24	前置碼偵測步驟2	…………………………………	18
圖2.25	前置碼偵測步驟3	…………………………………	19
圖2.26	Demodulation架構	…………………………………	20
圖2.27	Demodulator方塊圖	…………………………………	20
圖2.28	Deinterleaver方塊圖…………………………………	21
圖2.29	Deinterleaver動作時序圖……………………………	22
圖2.30	Deinterleaver波形模擬圖……………………………	22
圖2.31	Descrambler方塊圖	…………………………………	23
圖2.32	Descrambler動作時序圖……………………………	23
圖2.33	Descrambler波形模擬圖……………………………	24
圖2.34	Manchester Decoder方塊圖…………………………	24
圖2.35	Manchester Decoder動作時序圖……………………	24
圖2.36	Manchester Decoder波形模擬圖……………………	25
圖2.37	AWGN方塊圖……………………………………	26
圖2.38	AWGN與Pathfinder硬體實現結果比較圖	…………	27
圖3.1	(2,1,3) Convolutional Encoder……………………	29
圖3.2	(2,1,3) Convolutional Encoder狀態圖	…………	29
圖3.3	(2,1,3) Convolutional Encoder柵欄圖	…………	30
圖3.4	(2,1,3) Convolutional Encoder方塊圖	…………	30
圖3.5	(2,1,3) Convolutional Encoder動作時序圖………	31
圖3.6	(2,1,3) Convolutional Encoder波形模擬圖………	31
圖3.7	Viterbi Decoder架構圖………………………………	32
圖3.8	Viterbi Decoder方塊圖………………………………	33
圖3.9	Viterbi Decoder動作時序圖	………………………	33
圖3.10	Viterbi Decoder波形模擬圖	………………………	34
圖4.1	Stratix Edition—S80………………………………	35
圖4.2	實測架構1 (GFSK)	………………………………	39
圖4.3	實測架構2 (GFSK+FEC)……………………………	39
圖4.4	實測架構3 (GFSK+RF)………………………………	40
圖4.5	實測架構4 (GFSK+FEC+RF)…………………………	40
圖4.6	實測環境	……………………………………………	41
圖4.7	RF Module	…………………………………………	41
圖4.8	RF Sensitivity -65dBm~-85dBm，RF Module的輸出信號	………42
圖4.9	BER vs. SNR (架構1 vs.架構2)……………………	44
圖4.10	BER vs. Sensitivity (架構3 vs.架構4)…………	44
圖4.11	Low Data Rate時中頻降低之模擬結果………………	45

表目錄
表2.1	PN Sequence之I/O腳位定義	………………………	7
表2.2	Manchester Encode之I/O腳位定義…………………	9
表2.3	Scrambler之I/O腳位定義……………………………	11
表2.4	Interleaver之I/O腳位定義…………………………	13
表2.5	Demodulation之I/O腳位定義…………………………	20
表2.6	Deinterleaver之I/O腳位定義	………………………	21
表2.7	Descrambler之I/O腳位定義…………………………	23
表2.8	Manchester Decoder之I/O腳位定義…………………	25
表2.9	AWGN之I/O腳位定義	……………………………	27
表3.1	Convolutional Encoder之I/O腳位定義……………	31
表3.2	Viterbi Decoder之I/O腳位定義……………………	33
表4.1	硬體實現耗費之LE及記憶體	………………………	37
表4.2	實測架構	…………………………………………	38
表4.3	實測環境參數………………………………………	38
表4.4	BER實測結果(架構1 vs.架構2)	………………………	43
表4.5	BER實測結果(架構3 vs.架構4)	………………………	43

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