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系統識別號 U0002-2506201417530800
中文論文名稱 具有軌對軌輸出入信號之低功耗高增益運算放大器之設計
英文論文名稱 Design of Low-Power High-Gain Operational Amplifier with Rail-to-Rail Input and Output Ranges
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士在職專班
系所名稱(英) Department of Electrical Engineering
學年度 102
學期 2
出版年 103
研究生中文姓名 許媛雯
研究生英文姓名 Yuan-Wen Hsu
學號 795440303
學位類別 碩士
語文別 中文
口試日期 2014-06-17
論文頁數 53頁
口試委員 指導教授-郭建宏
委員-楊維斌
委員-饒建奇
委員-郭建宏
中文關鍵字 運算放大器  軌對軌  固定轉導  增益提高組態 
英文關鍵字 amplifier  rail-to-rail  constant-gm  gain-boosting 
學科別分類 學科別應用科學電機及電子
中文摘要 隨著時代的改變,運算放大器(Operational Amplifier)有各類型不同的應用與製程選擇,超大型積體電路(VLSI)與互補式金屬氧化性半導體(CMOS)在製程上不斷的改進,運算放大器因此在設計有較多選擇。在現代新的應用上傾向高增益、低功耗、全擺幅輸出入、高穩定度、高推力、低成本等需求,因此本文提供之運算放大器設計目標為儘量符合以上需求。
整體電路包含三大部分,第一部分為差動輸入級,含軌對軌輸入端及固定轉導控制器,第二部分為疊接增益級,含疊接組態、浮動電流源及增益提高組態之組合,第三部分為單端輸出級,為一AB類推挽放大器。最後目標為期望規格到達增益(Gain)為120dB以上,相位安全邊限(Phase Margin)為60°~63°左右,單增益頻寬(Unity-gain frequency)為1.5MHz,消耗功率(power consumption)為0.37mW左右,輸出入均可達最大擺幅,並可推動最高負載電容50pF或最低負載電阻10kΩ等。
本設計採用國家晶片系統設計中心(CIC) 0.35μm 2P4M CMOS製程,根據驗證結果,本設計的實際規格可以到達增益為123dB,相位安全邊限為61.4°,單增益頻寬為1.52MHz,消耗功率為0.37mW,輸出入擺幅可由最低0V到最高3.3V,並可穩定推動負載電容50pF或負載電阻10kΩ。
英文摘要 This thesis presents an operational amplifier which function could meet the new requirement of nowadays. Following the improvement of VLSI (Very Large Scale Integrated Circuits) design and CMOS (Complementary Metal Oxide Semiconductor) process, the design of OPA (Operational Amplifier) has many choices for different applications and purposes. The new tendency of OPA applications would be high gain, low power consumption, rail-to-rail input/output range, better stability, better driving capability and low cost, etc., which would be the goal of this proposed OPA to be designed.
The architecture of this proposed OPA includes 3 major stages: the first stage is the differential inputs stage combined with constant-gm controller; the second stage is the folded-cascode amplifier stage constructed of cascode, floating current source and gain boosting amplifiers; the third stage is the single-ended output stage consisted of a class AB push-pull amplifier. The goal of this OPA is to achieve that gain equals over 120dB, phase margin equals around 60°~63°, unity-gain frequency equals 1.5MHz, power consumption equals 0.37mW, the input/output range reaches the maximum, and the driving load is up to 50pF capacitor or lowest to 10kΩ resistor, etc.
The fabrication of this proposed OPA is implemented by the 0.35μm 2P4M CMOS process of CIC (Chip Implementation Center). The final result of this OPA is that gain equals 123dB, phase margin 61.4°, unity-gain frequency 1.52MHz, power consumption equals 0.37mW, the input/output range reaches from 0V to 3.3V, and the driving load is stable up to 50pF capacitor or lowest to 10kΩ resistor.
論文目次 中文摘要............................................I
英文摘要...........................................II
內文目錄..........................................III
圖表目錄..........................................VII

第一章 緒論……………………………………………………1
1.1研究背景與動機 …………………………………………1
1.2設計流程 …………………………………………………1
1.3論文架構 …………………………………………………3

第二章 具有軌對軌輸出入信號之低功耗高增益運算放大器之設計……………………………………………………………4
2.1 電流源 ……………………………………………………4
2.2 架構簡介 …………………………………………………5
2.3 偏壓電路 …………………………………………………7
2.3.1電流鏡與偏壓 ………………………………………7
2.3.2偏壓電路設計 ………………………………………9
2.3.3偏壓電路模擬結果 ………………………………10

第三章 差動輸入級…………………………………………11
3.1 軌對軌輸入原理 ………………………………………12
3.2 原始軌對軌輸入對轉導變化 …………………………13
3.3 固定轉導控制器原理 …………………………………15

第四章 疊接增益級…………………………………………18
4.1 折疊疊接放大器原理 …………………………………18
4.1.1疊接放大器 ………………………………………18
4.1.2折疊疊接放大器 …………………………………19
4.2 浮動電流源原理 ………………………………………21
4.2.1本文之浮動電流源 ………………………………21
4.2.2浮動電流源結構 …………………………………25
4.3 增益提高組態原理 ……………………………………26
4.3.1提高增益的方式 …………………………………26
4.3.2本文採用之增益提高組態 ………………………27
4.4 疊接增益級模擬結果 …………………………………30
第五章 單端輸出級…………………………………………32
5.1 AB 類推挽放大器………………………………………32
5.2 本文之AB類推挽式放大器……………………………33
5.3 雙級運算放大器 ………………………………………35
5.3.1米勒補償 …………………………………………35
5.3.2本文放大器使用之米勒補償 ……………………37
5.3.3浮動電流源變更為電阻之比較 …………………38
5.4 本文放大器之輸出模擬結果 …………………………39
5.4.1增益與頻寬 ………………………………………40
5.4.2共模排斥比 ………………………………………42
5.4.3供應電源排斥比 …………………………………42
5.4.4廻轉率 ……………………………………………43
5.4.5步級響應 …………………………………………45
5.4.6水平與垂直位移 …………………………………46
5.4.7消耗功率 …………………………………………46

第六章 結論…………………………………………………47
6.1 模擬與量測結果比較 …………………………………47
6.2 參考比較 ………………………………………………48

參考文獻………………………………………………………50

圖目錄
圖 1.1 運算放大器設計流程圖 …………………………………………2
圖 2.1 NMOS特性曲線圖…………………………………………………4
圖 2.2 PMOS特性曲線圖…………………………………………………5
圖 2.3 本文之運算放大器架構圖 ………………………………………6
圖 2.4 電流鏡參考電路圖 ………………………………………………8
圖 2.5 本文之偏壓電路設計圖 …………………………………………9
圖 2.6 偏壓電路模擬結果………………………………………………10
圖 3.1 (a)差動輸入(b)共模輸入………………………………………11
圖 3.2 單增益緩衝器……………………………………………………11
圖 3.3 (a)PMOS輸入對輸入範圍限制(b)NMOS輸入對輸入範圍限制.12
圖 3.4 軌對軌輸入………………………………………………………13
圖 3.5 原始軌對軌輸入對在共模輸入時的電流變化…………………14
圖 3.6 原始軌對軌輸入對在共模輸入時的轉導變化…………………14
圖 3.7 固定轉導控制器…………………………………………………16
圖 3.8 固定轉導控制器在共模輸入時的電流變化……………………17
圖 3.9 固定轉導控制器在共模輸入時的轉導變化……………………17
圖 4.1 疊接增益級………………………………………………………18
圖 4.2 疊接放大器(a)差動輸出(b)單端輸出之單增益緩衝器………19
圖 4.3 折疊疊接放大器…………………………………………………20
圖 4.4 單端輸出之折疊疊接放大器(a)二極體(b)寬擺幅……………21
圖 4.5 疊接組態與浮動電流源…………………………………………22
圖 4.6 二組折疊疊接放大器……………………………………………23
圖 4.7 共模輸入掃描(a)疊接組態(b)浮動電流源之電流變化………24
圖 4.8 共模輸入掃描(a)Vout1(b)Vout2之電壓變化 ………………24
圖 4.9 浮動電流源(a)輸出至下一級(b)負載效應……………………25
圖 4.10 提高輸出阻抗(a)原始疊接組態 (b)加上回授電路的組態…26
圖 4.11 NMOS輸入對增益提高組態(A1N) ………………………………27
圖 4.12 PMOS輸入對增益提高組態(A1P) ………………………………28
圖 4.13 疊接增益級全圖 ………………………………………………29
圖 4.14 折疊疊接放大器加上增益提高組態 …………………………30
圖 4.15 差動輸入掃描(a)輸入對(b)疊接組態之電流變化 …………31
圖 4.16 差動輸入掃描(a)浮動電流源(b)輸出之電流變化 …………31
圖 5.1 A/AB類放大器 …………………………………………………32
圖 5.2 單端輸出級………………………………………………………33
圖 5.3 (a)差動輸入與軌對軌輸出(b)輸出對增益的變化……………34
圖 5.4 輸出級之增益……………………………………………………34
圖 5.5 負回授系統………………………………………………………35
圖 5.6 雙級運算放大器之米勒補償……………………………………36
圖 5.7 米勒補償後之極點往原點移動…………………………………36
圖 5.8 使用米勒補償電容CC之比較,CL=50pF…………………………37
圖 5.9 使用電阻代替浮動電流源………………………………………38
圖 5.10使用電阻代替浮動電流源與米勒補償之變化 ………………39
圖 5.11本文之運算放大器 ……………………………………………40
圖 5.12 本文運算放大器之增益、相位、頻寬,CL=50pF………………40
圖 5.13 本文運算放大器之增益、相位、頻寬,CL=1pF…………………41
圖 5.14 本文運算放大器之增益、相位、頻寬,RL=10kΩ………………41
圖 5.15 本文運算放大器之共模排斥比(CMRR) ………………………42
圖 5.16 本文運算放大器之供應電源排斥比(PSRR+)…………………42
圖 5.17 本文運算放大器之供應電源排斥比(PSRR-)…………………43
圖 5.18 (a)步級輸入(b)本文運算放大器1V時之廻轉率……………44
圖 5.18 (c)本文運算放大器3.3V時之廻轉率 ………………………44
圖 5.19 本文運算放大器之100mV步級響應 …………………………45
圖 5.20 本文運算放大器之1V步級響應………………………………45
圖 5.21本文運算放大器之輸出水平與垂直位移 ……………………46

表目錄

表 6.1 本文運算放大器之模擬規格……………………………………47
表 6.2 (a)軌對軌運算放大器比較表[12]-[18]………………………49
表 6.2 (b)軌對軌運算放大器比較表[19]-[25]………………………49
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[13] V. Ivanov and S. Zhang, “250MHz CMOS Rail-to-Rail IO OpAmp: Structural Design Approach,” IEEE Proceedings of the 28th European Solid-State Circuits Conference, ESSCIRC, pp. 183-186, 2002.
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[15] J. M. Carrillo, J. F. Duque-Carrillo, G. Torelli, and J. L. Ausin, “Constant-gm Constant-Slew-Rate High-Bandwidth Low-Voltage Rail-to-Rail CMOS Input Stage for VLSI Cell Libraries,” IEEE International Symposium on Circuit and Systems, ISCAS, vol. 1, pp. I-165-I-168, May 2003
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