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系統識別號 U0002-2502202016061300
中文論文名稱 使用六位元逐次逼近式類比數位轉換器作量化器回授之高解析度低功耗離散時間二階三角積分調變器
英文論文名稱 Design of a High Resolution and Low Power Discrete-Time Second-order Delta Sigma Modulator with 6-bit SAR Feedback Quantizer
校院名稱 淡江大學
系所名稱(中) 電機工程學系機器人工程碩士班
系所名稱(英) Master’s Program In Robotics Engineering, Department Of Electrical And Computer Engineering
學年度 108
學期 1
出版年 109
研究生中文姓名 陳柏劭
研究生英文姓名 Po-Shao Chen
學號 605470292
學位類別 碩士
語文別 中文
口試日期 2020-01-08
論文頁數 61頁
口試委員 指導教授-江正雄
委員-吳紹懋
委員-楊維斌
委員-陳信良
中文關鍵字 離散時間  三角積分調變器  逐次逼近式類比數位轉換器之量化器 
英文關鍵字 Discrete-Time  Sigma Delta Modulator  SAR quantizer 
學科別分類
中文摘要 類比數位轉換器(Analog-to Digital-Converter, ADC)的應用十分廣泛,且擁有許多種類,如果考慮高解析度的應用,三角積分類比數位轉換器是最佳選擇。三角積分類比數位轉換器的核心是三角積分調變器(Delta-Sigma Modulator, DSM),為了達到更高的解析度,在設計上可以考慮提高DSM的階數或是量化器位元數,而後者的提升,會使得量化器的設計更來得不容易,且功耗要求更大。而如何在提高位元數的要求下,盡可能的設計出高解析度且低耗能的量化器,是本論文所探討之方向。

本研究為設計一個三角積分類比數位轉換器(DSM ADC),並結合逐次逼近式類比數位轉換器(SAR ADC)作為量化器使用。相較於一般使用快閃式類比數位轉換器(FLASH ADC)為量化器,使用SAR ADC可以擁有更低的功耗,且FLASH ADC在高位元的考量下,設計不易且效能不佳,使用SAR ADC可以解決此問題,在高位元量化器的DSM實現下,更能凸顯出SAR ADC量化器及Flash ADC量化器的優劣性。

本論文所提出的三角積分調變器,使用UMC 0.18m CMOS製程,其作用電壓為1.8V,頻寬為25kHz,取樣頻率為3.2MHz,系統電壓操作範圍為0.45V 至 1.35V,SNDR可達到101.88 dB,平均功耗為833uW。
英文摘要 The applications of Analog-to-Digital Converter (ADC) are very broad, and it has various types. When considering high resolution applications, Delta-Sigma Analog-to-Digital Converter must be the best choice. Delta-Sigma Modulator (DSM) is the core of Delta-Sigma Analog-to-Digital Converter. As for high resolution Delta-Sigma ADC considerations, there are two approaches to achieve this goal. One is to increase the order and the other is to increase quantizer bits of the SDM. The latter method will make the quantizer design become more difficult and consume more power. This research work will investigate how to design high resolution and low power quantizer while increasing the bits in the quantizer.

This work designs a high resolution DSM combined with Successive Approximation Register (SAR) ADC as the quantizer. Compared with using conventional FLASH ADC as the quantizer in a DSM, using SAR ADC will consume less power. For circuit implementation, it is difficult to design a high bit FLASH ADC, while using SAR ADC will resolve these problems. Under high bit DSM, the strength and weakness between SAR quantizer and Flash quantizer will significantly arise.

The proposed DSM was designed by UMC 0.18m CMOS technology. The chip has functional voltage of 1.8V, bandwidth of 25kHz, sampling frequency of 3.2MHz, system operation voltage ranging from 0.45V to 1.35V, SNDR of 101.88 dB and power consumption of 833uW.
論文目次 中文提要 I
英文提要 II
目錄 III
圖目錄 VII
表目錄 X
第1章 概論 1
1.1 研究背景與動機 1
1.2 設計流程 2
1.3 論文架構 3
第2章 類比數位轉換器簡介 4
2.1 前言 4
2.2 類比數位轉換器架構 4
2.2.1 快閃式類比數位轉換器(Flash ADC) 4
2.2.2 管線式類比數位轉換器(Pipeline ADC) 5
2.2.3 逐次逼近暫存器式類比數位轉換器(SAR ADC) 6
2.2.4 三角積分調變器(Delta-Sigma Modulator, DSM) 7
2.3 類比數位轉換器參數定義 7
2.3.1 解析度(Resolution) 7
2.3.2 量化誤差(Quantization Error) 8
2.3.3 信號雜訊比(SNR) 9
2.3.4 信號對雜訊和失真比(SNDR) 9
2.3.5 無雜散動態範圍(Spurious-Free Dynamic Range, SFDR) 10
2.3.6 有效位元(Effective Number of Bits, ENOB) 10
2.3.7 微分非線性(Differential Non-Linearity, DNL) 10
2.3.8 積分非線性(Integral Non-Linearity,INL) 11
2.4 ADC架構的比較 12
第3章 三角積分調變器 16
3.1 三角積分調變器簡介 16
3.2 三角積分調變器架構 18
3.2.1 單一迴路架構 18
3.2.2 多迴路架構 19
3.3 量化器 19
3.4 奈奎氏取樣定理 21
3.5 超取樣技術 22
3.6 雜訊移頻 24
3.6.1 一階之雜訊移頻 25
3.6.2 二階之雜訊移頻 27
第4章 系統設計與前模擬 29
4.1 系統架構 29
4.2 系統架構之模擬驗證 29
4.3 電路設計與模擬 31
4.4 放大器 (OPERATIONAL AMPLIFIER) 33
4.4.1 二級差動運算放大器 33
4.4.2 共模迴授電路 (CMFB) 35
4.5 控制時序產生之電路 36
4.5.1 除頻器 (Freguency divider) 36
4.5.2 非重疊時脈產生器(Nonoverlapping) 37
4.5.3 完整之系統控制時序 38
4.6 積分器 (INTEGRATOR) 39
4.6.1 交換式電容電路 39
4.6.2 積分器電路 40
4.7 加法器 (SUMMER) 41
4.8 迴授部分之積分器 (INTEGRATOR WITH DAC) 43
4.9 SAR ADC 電路架構 45
4.9.1 SAR ADC 系統架構 45
4.9.2 數位類比轉換器 (DAC) 46
4.9.3 比較器 (Comparator) 47
4.9.4 SAR控制電路 (SAR LOGIC) 49
第5章 佈局與結果比較 50
5.1 佈局圖 50
5.2 模擬結果 52
5.3 模擬結果比較 55
5.4 量測考量與結果 56
第6章 結論 58
6.1 結論與未來展望 58
參考文獻 59

圖1.1晶片設計流程圖 2
圖2.1 Flash ADC 5
圖2.2 Pipeline ADC 系統架構 6
圖2.3 SAR ADC系統架構 6
圖2.4 DSM轉移函式 7
圖2.5量化誤差之機率密度函數分布 8
圖2.6二級式高解析ADC架構圖 13
圖2.7混合型高解析ADC架構 14
圖2.8各ADC架構之應用範圍 15
圖3.1三角積分調變器區塊圖 16
圖3.2三角積分調變器之架構 17
圖3.3 (a)CIFB (b)CIFF架構 18
圖3.4簡單之多級串接架構 19
圖3.5 Mid-rise量化和量化誤差 20
圖3.6 Mid-tread量化和量化誤差 21
圖3.7奈奎式取樣率之頻譜 22
圖3.8超取樣轉換器之架構 22
圖3.9經由低通濾波器後之功率頻譜密度 23
圖3.10三角積分調變器之數學模型 24
圖3.11一階之三角積分調變器架構 25
圖3.12傳統二階三角積分調變器 27
圖3.13一階及二階雜訊移頻之功率頻譜密度 28
圖4.1電路系統架構 30
圖4.2功率頻譜密度圖 30
圖4.3動態分析 31
圖4.4混合型類比數位轉換器電路 32
圖4.5二級差動運算放大器 33
圖4.6放大器模擬結果(波德圖) 35
圖4.7交換式電容共模迴授電路 35
圖4.8除頻器電路 36
圖4. 9除頻器模擬結果 36
圖4. 10非重疊時脈產生器電路 37
圖4. 11非重疊時脈 38
圖4. 12系統時序控制 38
圖4. 13交換式電容電路 39
圖4. 14互補式開關電路 39
圖4.15積分器電路 40
圖4.16反向延遲加法器電路 42
圖4.17迴授部分之積分器電路 44
圖4.18 SAR ADC 系統架構圖 45
圖4.19 SAR ADC 模擬結果(頻譜圖) 45
圖4.20 CDAC電路圖 46
圖4.21 4輸入動態比較器 47
圖4.22比較器遲滯圖 48
圖4.23位移式暫存器電路 49
圖5.1佈局設計圖 50
圖5.2實際佈局圖 51
圖5. 3完整電路Presim模擬結果之頻譜圖(TT_25°) 52
圖5. 4完整電路Presim模擬結果之頻譜圖(其他模擬環境) 53
圖5. 5 完整電路Prosim模擬結果之頻譜圖(TT_25°) 54
圖5. 6完整電路Prosim模擬結果之頻譜圖(其他模擬環境) 54
圖5. 7量測環境之設定 56
圖5. 8濾波電路及偏壓電路(a)Filter tank(b)LM317(c)OP27 57

表2. 1各類ADC特性比較表 13
表4. 1 系統規格 30
表4. 2 放大器設計規格 33
表4. 3 放大器模擬結果 34
表4. 4 遲滯表 48
表5. 1 Presim模擬結果 52
表5. 2 prosim模擬結果 53
表5. 3 模擬結果比較表 55


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[7]Y. Geerts, M. S. J. Steyaert and W. Sansen, "A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC," in IEEE Journal of Solid-State Circuits, vol. 35, no. 12, pp. 1829-1840, Dec. 2000
[8]Gil-cho Ahn et al., "A 0.6V 82dB /spl Delta//spl Sigma/ audio ADC using switched-RC integrators," ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., San Francisco, CA, 2005, pp. 166-591 Vol. 1
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