電流導向式數位類比轉換器在寬頻帶的應用上因為具有很高的無突波動態範圍，在動態元件匹配方法裡，資料權重平均法(DWA)被廣泛應用在超取樣技術中。為提高效能，奈奎斯特頻帶技術的電流導向式數位類比轉換器會使用隨機的方法，再配合適當的佈局，來降低製程上所引起的電晶體不匹配效應，也可以降低整體數位類比轉換器的面積。
  本論文提出一個10位元100MHz電流導向式數位類比轉換器的設計與實現，此電流導向式數位類比轉換器的輸出不需要額外的緩衝器，所以可以達成低功耗、高速及高解析度的規格；然而數位類比轉換器在動態及靜態的表現中會受到製程上不匹配的影響，因此，本論文採用偽隨機動態元件匹配技術來改善其在製程上的影響，此隨機產生器可控制最高有效位元(MSB)的隨機選擇，讓元件不匹配所造成的諧波(Harmonics)可以被大量降低。

The current-steering digital to analog converter (DAC) is widely used in wideband applications, where a high spurious-free dynamic rang (SFDR) is particularly preferred. As a DEM method, the method of data-weighted average (DWA) is widely used for oversampling rate applications. On the other hand, in Nyquist rate applications, a random multiplying method is used for current-steering DAC. Together with a proper layout switching scheme, the effect of the serious mismatch caused by transistors can be reduced, and a small-area DAC can be achieved.

This work presents a 10-bit 100MHz digital-to-analog converter (DAC) by using a current-steering architecture. The output of the DAC does not require an extra output buffer to convert current to voltage so as to achieve lower power consumption and to suit for high speed and high resolution applications. However, these current-steering DACs suffer from the process mismatch which limits both the static and dynamic performance. To solve the drawback, this work employs a pseudo-random structure to improve the element selecting. The random generator controls the selection of the element in the MSB part, and therefore the harmonics caused by mismatch problem can be mitigated.

中文提要	I
英文提要	II
目錄	III
圖目錄	V
表目錄	VII
第1章	緒論	1
1.1	研究背景與動機	1
1.2	論文架構	2
1.3	設計流程	3
第2章	數位類比轉換器基本架構	4
2.1	數位類比轉換器簡介	4
2.2	理想數位類比轉換器	5
2.3	數位類比轉換器規格參數	5
2.3.1	靜態參數	5
2.3.2	動態參數	11
2.3.3	轉換參數	12
2.4	數位類比轉換器架構	14
2.4.1	電阻串列式數位類比轉換器(Resistor string DAC):	15
2.4.2	二進位權重電阻式數位類比轉換器(Binary-weighted resistor DAC):	16
2.4.3	R-2R電阻階梯式數位類比轉換器(R-2R ladders DAC):	17
2.4.4	電容電荷重新分布式數位類比轉換器(Charge redistribution DAC):	18
2.4.5	溫度計編碼電流源切換式(Current mode thermometer code DAC):	20
2.4.6	混合式數位類比轉換器(Hybrid architecture DAC):	22
2.5	結論	23
第3章	電流式數位類比轉換器非理想效應	24
3.1	電流源不匹配	25
3.1.1	隨機誤差(Random error)	25
3.1.2	梯度誤差(Graded error)	28
3.2	電流源的有限輸出阻抗	30
3.3	電壓偏移	33
3.4	結論	35
第4章	電路設計與佈局模擬	36
4.1	數位類比轉換器架構	36
4.1.1	混合式數位類比轉換器	36
4.1.2	10位元數位類比轉換器架構圖	38
4.2	數位電路	39
4.2.1	溫度計解碼器	39
4.2.2	隨機電路(Randomizer)	42
4.2.3	高速門閂電路(High Speed Latch)	44
4.3	類比電路	46
4.3.1	電流單元	46
4.3.2	參考偏壓電路(Bias)	48
4.4	晶片佈局	49
4.5	模擬結果	51
4.6	結論	55
第5章	量測設定	56
5.1	量測環境設定	56
第6章	結論與未來工作展望	57
6.1	結論	57
6.2	未來展望	57
參考文獻(REFERENCES)	58
 
圖目錄
圖1. 1 電流導向式數位類比轉換器	2
圖1. 2設計流程	3
圖2. 1 數位類比轉換過程圖	4
圖2. 2 偏移誤差	7
圖2. 3 增益誤差	8
圖2. 4 微分非線性誤差	9
圖2. 5 積分非線性誤差	10
圖2. 6 非單調性數位類比轉換器	11
圖2. 7 突波	12
圖2. 8 數位類比轉換器快速傅立葉轉換頻譜圖	13
圖2. 9 數位類比轉換器快速傅立葉轉換頻譜圖	15
圖2. 10 二進位權重電阻式數位類比轉換器	16
圖2. 11 R-2R電阻階梯式架構數位類比轉換器	18
圖2. 12 電容電荷重新分布式數位類比轉換器	19
圖2. 13 N位元溫度計編碼數位類比轉換器	21
圖2. 14 N位元混合式數位類比轉換器	22
圖3. 1 差動輸出電流式數位類比轉換器	24
圖3. 2 理想MOS電流源與製程中發生隨機不匹配	26
圖3. 3 電流源陣列外圍等效相仿電流源	28
圖3. 4  (A)線性誤差(FIRST ORDER) (B)二階誤差(SECOND ORDER)	30
圖3. 5 電流源輸出阻抗	31
圖3. 6 電壓偏移示意圖	33
圖3. 7 低準位交錯點開關信號	34

圖4. 1 二進位加權碼架構與溫度計編碼架構比較圖	36
圖4. 2 十位元數位類比轉換器架構圖	38
圖4. 3  3位元二進位權重碼轉溫度計編碼電路圖	41
圖4. 4 矩陣式行列式解碼器溫度計編碼器	41
圖4. 5 ROW-COLUMN DECODER	42
圖4. 6 多工器陣列	43
圖4. 7 亂數產生器	43
圖4. 8 門閂電路	44
圖4. 9 低交越點高速門閂電路模擬圖	45
圖4. 10 電流源設計流程	47
圖4. 11 疊接式電流源	48
圖4. 12 電流源偏壓電路圖	49
圖4. 13 數位類比轉換器佈局圖	50
圖4. 14  取樣1024點 SIN波頻譜，FS=100MHZ  AND  FIN=1MHZ	52
圖4. 15 取樣128點 SIN波頻譜，FS=100MHZ  AND  FIN=8.59MHZ	52
圖4. 16 取樣256點 SIN波頻譜，FS=100MHZ  AND  FIN=8.59MHZ	52
圖4. 17 POST-SIM SIN波頻譜，FS=100MHZ  AND  FIN=8.59MHZ	53
圖4. 18 微非線性誤差DNL小於0.4LSB	53
圖4. 19積分非線性誤差INL小於0.04LSB	54

圖5. 1 量測示意圖	56

 
表目錄

表2. 1 三位元二進碼與溫度計編碼對照表	21
表4. 1 二進位碼與溫度計編碼及混合式數位類比轉換器比較	37
表4. 2  3位元溫度計解碼與二進位權重碼對照表	40
表4. 3 製成變異模擬表	54
表4. 4文獻比較表	55

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