論文提要內容：  	
     系統晶片會隨著製程、供應電壓定與溫度偏異而產生飄移，電路上會產生非理想的偏異，會造成系統上的不穩定，進而造成晶片的不正常工作，更嚴重而導致晶片的損壞，如何設計出一不隨製程、電壓與溫度變異且低功率消耗的穩壓器便是研究中一個重要的議題，在電路設計上使用數位電路才取代誤差放大器，因此，此論文目標為設計出一個使用連續漸近式類比數位轉換器架構之低壓降線性穩壓器。
低壓降線性穩壓器有幾項主要考量的特性參數: (1) 輸出電壓差(△V)與靜態電流(Quiescent Current, Iq) (2) 線性調節率(Line Regulation, LNR) (3)負載調節率(Load Regulation, LDR)；這些參數都與負載電流、精準度、穩壓時間有著密不可分的關係。整體電路可分為三大部分，第一部分為利用8位元連續漸近式類比數位轉換器架構，第二部分為功率電晶體的切換，而第三部分為比較器。
    低壓降線性穩壓器電路的設計，產生一電壓誤差10%的電壓與一最低與最高的可承受電流，而這兩電壓與電流經由功率電晶體後，最後輸出電壓還能穩定在固定的電壓，利用連續漸近式類比數位轉換器的訊號來控制功率電晶體以達到穩定的輸出電壓，並且降低在穩態中，所消耗的靜態電流。首先利用比較器來比較輸入電壓與原供應電壓的誤差來控制回授電阻的切換。第二利用電流的變化來切換回授電阻並控制功率電晶體的開或關。最後第三點，在設計連續漸近式類比數位轉換器架構和比較器部分，盡量降低DC電流消耗以節省整體的電流消耗。

Abstract:
Soc circuit will produce a non-ideal effect with process, supply voltage, and temperature, which cause the chip does not work or lead to damage to the chip in serious. And how to design a low power consumption of the circuit is an important issue.
We will design a circuit which use of the successive approximation analog to digital converter to replace error amplifier. Therefore, this paper the target for the design of a low dropout linear regulator with successive approximation analog to digital converter architecture.
There are several key considerations of low dropout linear regulator characteristic parameters: (1) The output voltage difference (△ V) (2) linear regulator with quiescent current (The Quiescent Current, Iq) rate (Line Regulation, LNR) (3 ) load Regulation (Load Regulation, LDR); these parameters has a close relationship with the load current, precision, settling time. The circuit can be divided into three parts, the first part of the 8-bit successive approximation analog-to-digital converter architecture, the second part is the switching of the power transistor, the last part is the comparator.
Using the signal from SAR ADC to control the power transistor to achieve the output voltage, and reduce the quiescent current in the steady state. First, compare the input voltage and the original supply voltage to control the feedback resistor switching. Second, current changes will control turn on the power transistor or turn off the power transistor.
The simulation results are based on 0.18μm CMOS process. The current efficiency is 99.94%. Moreover, the quiescent current of the  circuit is 15.8μA in a heavy load condition.

目錄
中文摘要	I
英文摘要	II
內文目錄	III
圖目錄	VI
表目錄	IX

第一章  緒論	1
1.1 研究背景與動機	1
1.2 設計流程與應用	2
1.3 論文架構	4
第二章  低壓降線性穩壓器	5
2.1低壓降線性穩壓器概論	5
2.2低壓降線性穩壓器之特性參數	6
2.2.1壓降電壓與靜態電流	7
2.2.2線性調節率與負载調節率	8
2.3數位式低壓降線性穩壓器	11
2.4文獻回顧與探討	11
2.4.1串列輸入並列輸出雙向移位暫存器	11
2.4.2應用於40nm製程具快速暫態響應之數位LDO	12
2.4.3具數位式控制器之電壓線性穩壓器	13
第三章  類比數位轉換器的基本原理與架構分析	15
3.1類比數位轉換器架構介紹與分析	15
3.1.1快閃式類比數位轉換器	15
3.1.2管線式類比數位轉換器	16
3.1.3連續漸近式類比數位轉換器	17
3.1.3.1二位元搜尋演算法	18
3.1.4積分式類比數位轉換器	19
3.2類比數位轉換器基本原理	20
3.2.1解析度	21
3.2.2最小有效位元	22
3.2.3量化誤差	22
3.2.4缺碼	23
3.2.5微分非線性誤差	23
3.2.6積分非線性誤差	23
3.2.7信號雜訊比	24
3.2.8有效位元	25
3.2.9高取樣定理	26
3.3數位類比轉換器電路設計	27
3.3.1二位元加權電阻式數位類比轉換器	27
3.3.2 R-2R階梯式數位類比轉換器	28
3.3.3電容式數位類比轉換器	29
第四章  連續漸近式類比數位轉換器	31
4.1 連續漸近式類比數位轉換器基本架構	31
4.2追蹤保持電路	32
4.2.1取樣NMOS開關	32
4.2.2取樣CMOS開關	33
4.3比較器電路設計	35
4.4連續漸近存式控制器之電路設計	36
4.5數位類比轉換器架構	40
第五章  連續漸近式類比數位轉換器之低壓降線性穩壓器	41
5.1 數位式低壓降線性穩壓器設計	41
5.2 連續漸近式類比數位轉換器架構介紹	42
5.2.1比較器	42
5.2.2應用於線性調節率之比較器	42
5.2.3功率電晶體的控制	43
5.3 電路模擬與佈局	43
5.4 量測考量與結果	59
第六章  結論	61
6.1結論與未來展望	61
參考文獻	62

圖目錄

圖1.1晶片設計流程圖	3
圖2.1傳統低壓降線性穩壓器之電路圖	5
圖2.2低壓降線性穩壓器之輸出/入電壓曲線圖	7
圖2.3靜態電流示意圖	8
圖2.4低壓降線性穩壓器之線性調節率示意圖	9
圖2.5負載調節率示意圖	10
圖2.6串列輸入並列輸出雙向移位暫存器	12
圖2.7快速暫態響應之數位LDO	13
圖2.8數位式控制器之電壓線性穩壓器	14
圖3.1快閃式類比數位轉換器架構圖	16
圖3.2管線式類比數位轉換器	17
圖3.3連續漸近式類比數位轉換器	18
圖3.4數位類比轉換器輸出電壓變化圖	19
圖3.5 SAR ADC 轉換流程圖	19
圖3.6積分式類比數位轉換器	20
圖3.7類比數位轉換器資料轉換過程	21
圖3.8理想的3位元ADC類比數位轉換關係	21
圖3.9轉換特性	22
圖3.10 ADC之量化誤差	23
圖3.11 INL、DNL示意	24
圖3.12量化雜訊功率頻譜密度圖	27
圖3.13二元加權電阻式數位類比轉換器	28
圖3.14 R-2R階梯式數位類比轉換器	29
圖3.15電容式數位類比轉換器	30
圖4.1連續漸近式類比數位轉換器方塊圖	31
圖4.2取樣NMOS開關	33
圖4.3 CMOS互補式開關	34
圖4.4電荷注入效應	34
圖4.5摺疊疊接運算放大電路	35
圖4.6使用高壓MOS之摺疊疊接運算放大電路	36
圖4.7一般連續漸近式暫存控制器	37
圖4.8 non-redundant successive approximation register架構	38
圖4.9 N-th Flip-Flop 方塊圖	38
圖4.10電容式數位類比轉換器	40
圖5.1連續漸近式類比數位轉換器之低壓降線性穩壓器	41
圖5.2功率電晶體控制單元	43
圖5.3線性調節率與附載調節率架構圖	44
圖5.4(a) 比較器遲滯(TT)	45
圖5.4(b) 比較器遲滯(FF)	45
圖5.4(c) 比較器遲滯(SS)	46
圖5.5連續漸近式類比數位轉換器模擬結果	46
圖5.6(a) 重載穩態模擬結果(TT)	47
圖5.6(b) 重載穩態模擬結果(FF)	47
圖5.6(c) 重載穩態模擬結果(SS)	48
圖5.7(a) 輕載穩態模擬結果(TT)	48
圖5.7(b) 輕載穩態模擬結果(FF)	49
圖5.7(c) 輕載穩態模擬結果(SS)	49
圖5.8(a) 線性調節率模擬圖(TT)	50
圖5.8(b) 線性調節率模擬圖(FF)	50
圖5.8(c) 線性調節率模擬圖(SS)	51
圖5.9(a) 載調節率模擬圖(TT)	52
圖5.9(b) 載調節率模擬圖(FF)	52
圖5.9(c) 載調節率模擬圖(SS)	53
圖5.10電路佈局圖	54
圖5.11電路佈局示意圖	54
圖5.12(a) post-layout simulation線性調節率模擬圖(TT)	55
圖5.12(b) post-layout simulation線性調節率模擬圖(FF)	55
圖5.12(c) post-layout simulation線性調節率模擬圖(SS)	56
圖5.13(a) post-layout simulation負載調節率模擬圖TT)	57
圖5.13(b) post-layout simulation負載調節率模擬圖(FF)	57
圖5.13(c) post-layout simulation負載調節率模擬圖(SS)	58
圖5.14量測儀器示意圖	59
圖5.15 Bonding wire之模型	59
圖5.16 輕載穩態電壓量測圖(1mA)	60

表目錄

表1.1傳統線性穩壓器與數位式穩壓器之特性	2
表2.1文獻比較表	14
表3.1類比數位轉換器架構分析	15
表4.1八位元連續漸近式控制器執行動作順序	39
表5.1預計規格表	44
表5.2 specification & pre-sim. 比較結果	53
表5.3 Specification, pre-sim.與post-sim.比較結果	58

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