近年來物連網的興起，無線通訊能力在物連網中是一重要因素，藉由無線感測網路的偵測，感測器才能與資料中心溝通；然而在無線感測網路系統中，無線接收器與發射器耗能高達總能量的90%， 因此超低功耗收發器是延長壽命一大關鍵。

目前的感測器皆為電池所提供，為了延長感測器的生命，幾乎都是以減少工作週期來增加壽命，但是接收器卻無法以此方法來達到節能的效果，因為當發射器發送訊息而接收器卻在休眠，會造成傳送失敗，所以用這種方式的收發器需要克服同步的問題，最近的技術是使用一輔助接收器，稱為喚醒接收器，喚醒接收器能夠克服上述困境。

近年來 注入鎖定(Injection-locked)的技術大量的使用於OOK或FSK的超低功耗接收器上，相較於FSK，OOK一般適用於短距離無線運用，以及在發送 '0' 時節省發送功率。Injection-locked的靈敏度保持在最高值，才能確保喚醒接收器在最高的靈敏度，以OOK為調變的接收器上，當接收器接收到 '1' 的訊號時，注入鎖定震盪器會輸出最大的電壓擺幅；反之，當接收訊號為 '0' 時，注入鎖定震盪器沒有輸出擺幅。此外，接收器所接收的訊號強弱會隨著與發射器的距離不同而改變，為了達到省電的目的，此論文提出了一利用數位方式完成的校正機制，藉由控制注入鎖定震盪器電流，來確保注入鎖定震盪器在製程、溫度、電壓改變下能夠正常運作，以及優化接收不同強度訊號時之功耗。

在校正電路方面，是利用SAR(Successive approximation)邏輯來控制注入鎖定震盪器的功耗。首先發射器會先傳送一連串足夠的 '1' 訊號來校正電路，若接收端接收到OOK訊號為 '1' 使得注入鎖定震盪器振盪，振盪訊號藉由波峰偵測器轉為直流電壓，再與比較器之參考電壓做比較會得到 '1' 的輸出結果，邏輯控制會繼續SAR搜尋，直到接收訊號'1'時振盪器不再震盪結束搜尋，相反的，若接收'1'訊號振盪器無法使震盪器振盪，則邏輯控制執行SAR搜尋，直到震盪器振盪。結束SAR搜尋後，數位控制會找到一個數位控制碼Dlow，Dlow是在接收訊號為'1'時能夠維持振盪的最低的數位控制碼。在傳送一連串的'1'訊號後是一連串的'0'訊號，邏輯控制執行SAR搜尋，搜尋到數位控制碼Dhigh，Dhigh是在接收訊號為'0'時能無法振盪的最高的數位控制碼。在Dlow與Dhigh區間是能夠確保振盪器在製程、電壓、溫度及接收訊號強度下能夠良好的運作，Dlow與Dhigh中間值則是我們所需之最安全的操作點。

本論文使用UMC18製程實現出具數位輔助注入鎖定校正之超低功耗喚醒接收器，本論文接收器消耗23.9μW時靈敏度為-63.7 dBm，此時傳輸速度為為33 kb/s，此時電路接收每單位資料所需之能源消耗為0.72 nJ/bit。

In recent years, injection-locked has been used extensively on ultra low-power OOK/FSK receiver. Compared to FSK, OOK is generally suitable for short-range wireless applications, and save power when sending digital signal '0'.Sensitivity of the injection-locked oscillator is maximized to ensure the entire wake-up receiver has a maximized sensitivity. For an OOK wake-up receiver, as data ‘1’ is received, the output voltage swing of the injection-locked oscillator should be maximized. On the contrary, as data ‘0’ is received, the injection-locked oscillator should output no voltage swing.
  In the aspect of calibration, we use SAR (Successive approximation) logic to control the power consumption of the injection-locked oscillator. The transmitter transmitted a series of data '1' in the preamble of a transmitted data frame. The length of the series of data '1' is long enough for performing the calibration. If the received OOK signal with a data of '1' let the injection-locked oscillator output a oscillating signal. The oscillating signal will be converted into a DC voltage by the envelope detector. After comparing the output DC voltage of the envelope detector with a pre-defined threshold voltage, the comparator outputs a data of '1'. Then the control logic performs the SAR search until the injection-locked oscillator stop oscillation under the data of '1' is received. On the contrary, if the injection-locked oscillator is not oscillated, the comparator outputs a data of '0' and  the control logic performs the SAR search to make the injection-locked oscillator under oscillation. After the SAR search, the lowest digital code (Dlow) for maintaining the injection-locked oscillator oscillating under received a data of '1' is found. The data after a series of '1' in the preamble of the transmitted data frame is a series of '0'. Then the control logic performs the SAR search to find the highest digital code (Dhigh) for maintaining the injection-locked oscillator not to oscillate under received a data of '0'. As shown in Fig. 3, the control code between the Dhigh and the Dlow can guarantee the injection-locked oscillator operating well under the condition of process, voltage, temperature (PVT) and the received signal strength. For having a largest safe window of operation, the middle code between the Dhigh and the Dlow can be chose.
  The digital auxiliary injection-locked calibration for ultra-low-power wake-up receiver is implement in UMC 0.18 µm CMOS process with supply voltage of 1.8 V. Under a power consumption of 23.9μW, the receiver has a sensitivity of -63.7 dBm and a energy consumption per received bit of 0.72 nJ/bit.

目錄
致謝..............................................................................................I
中文摘要...................................................................................II
ABSTRACT	III
目錄.............................................................................................IV
圖目錄.......................................................................................XII
表目錄.......................................................................................X
第一章	緒論	1
1.1  研究背景	1
1.2  研究動機	2
1.3  論文架構	3
第二章	開關鍵控喚醒接收器系統考量	4
2.1  接收器電路之類別與介紹	4
2.2  開關鍵控解調之類別與介紹	8
2.3  具校正之注入鎖定分頻器	13
第三章	注入鎖定喚醒接收器校正	14
3.1  電路校正系統	14
3.2  數位/類比轉換器(DAC)	16
3.2.1  電阻式	17
3.2.2  二進位加權電流式	18
3.3  搜尋法	19
3.3.1 循序搜尋法	20
3.3.2 二分搜尋法	20
3.3.3 二元樹搜尋法	21
第四章  超低功耗喚醒接收器電路設計	22
4.1  注入鎖定之超低功耗喚醒接收器	22
4.1.1  低雜訊放大器(Low Noise Amplifier, LNA)	22
4.1.1.1  放大器輸入端匹配	23
4.1.1.2  放大器雜訊分析	24
4.1.2  振盪器	27
4.1.2.1  注入鎖定分頻振盪器	28
4.1.3  波峰偵測器	33
4.1.4  比較器	33
4.2  電路模擬結果	37
4.2.1  超低功耗注入鎖定之喚醒接收器模擬結果	37
4.2.2   7 bits數位類比轉換器模擬結果	40
4.3  電路佈局	45
第五章  電路量測	46
5.1量測方式	46
第六章  結論與未來展望	51
參考文獻(References)	52
附錄Ａ......................................................................................................53









圖目錄
圖2. 1超再生接收器前端電路架構[1]	5
圖2. 2 ASK超低功耗無線傳輸晶片電路架構[2]	6
圖2. 3 FSK低超功耗接收器完整架構圖[3]	7
圖2. 4 ASK同步解調系統	9
圖2. 5 非相干解調系統	9
圖2. 6 OOK解調之接收器[4]	10
圖2. 7 利用INJECTION LOCKED FREQUENCY DIVIDER達成頻率轉振幅之目的以進行解調[5]	11
圖2. 8能解調OOK/FSK/PSK之超低功耗喚醒接收器之完整架構圖[6]	11
圖2. 9 (A) OOK、(B) FSK及(C)PSK解調原理[6]	12

圖3.1喚醒接收器之解調系統	15
圖3. 3 3BIT電阻串式數位類比轉換器	18
圖3. 4 N位元二進位加權電流式數位類比轉換器	19
圖3. 5二分搜尋法範例	20
圖3. 6三層二元搜尋樹範例	21

圖4. 1注入鎖定之超低功耗喚醒接收器架構	22
圖4. 2(A)低雜訊放大器；(B)電晶體M1之小訊號等效電路	23
圖4. 3 共源級放大器主要雜訊等效電路圖	25
圖4. 4當RL + RG << RS後等效電路圖	26
圖4. 6回授系統	28
圖4. 7使用主動電路提供負阻	29
圖4. 8串聯結合轉換為並聯結合	29
圖4. 9轉為三個並聯元件	29
圖4. 10交錯偶合對	31
圖4. 11交錯偶合對之等效電路	31
圖4. 12注入鎖定振盪器電路圖	32
圖4. 13波峰偵測器電路	33
圖4. 14 RC充放電過程	33
圖4. 15比較器	34
圖4. 16比較器VOUT與VIN關係圖	34
圖4. 17電流單元之電路架構	36
圖4. 18七位元之數位類比轉換器之電路架構	37
圖4. 19 LNA之模擬(A)S11;(B)增益;(C)雜訊指數	39
圖4. 20接收器於最高傳輸速度級最高靈敏度之模擬	39
圖4. 21喚醒接收器的靈敏度、功耗及校正輸出電壓關係圖	40
圖4. 22七位元數位類比轉換器模擬圖(TT, 25度)	41
圖4. 23七位元數位類比轉換器模擬圖(FF, 0度)	42
圖4. 24七位元數位類比轉換器模擬圖(SS, 75度)	42
圖4. 25電路佈局相對位置圖	45
圖4. 26電路佈局圖	45

圖5. 1阻抗匹配量測示意圖	46
圖5. 2接收器解調量測示意圖	47
圖5. 3數位校正示意圖	48
圖5. 4晶片微影圖	49
圖5. 5 PCB照相	50










表目錄
表2. 1ASK,FSK文獻比較表	8
表4. 1參考文獻規格比較表	44

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