本文是提出一可程式規劃系統晶片(System On Program Chip, SOPC) 之系統架構，針對粒子濾波器演算法，利用FPGA(Field Programming Gate Array)的硬體電路優勢，以軟硬體協同設計(HW/SW co-design)之方式實現硬體加速之功能，提升之演算法執行效率。藉由軟硬體緊密的合作，可以加快執行速度，也由於有彈性的設計方式，使得在解決各種問題時不需要重新設計硬體。最後，本文將以該軟硬體協同設計方式實現之粒子濾波器，配合多主從系統架構設計一物體影像即時追蹤系統，以驗證系統之性能表現。

This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve the execution performance of particle filter (PF) for embedded applications. Based on modular design architecture, a particle updating accelerator module via hardware implementation for updating particles and a weight evaluation module implemented on a soft-cored processor for calculating weighting for each particle are respectively designed and work closely together to accelerate the execution process. Thanks to a flexible design, the proposed approach can tackle various problems of embedded applications without the need for hardware redesign. Experiment results have demonstrated that the proposed HW/SW co-deign approach to realize particle filters has good computational efficiency to achieve a high-quality solution effectively. Finally, we realize the proposed particle filter with multi-master system architecture design to establish an image processing system for real-time object tracking

中文摘要I
英文摘要II
目錄	III
圖目錄	VI
表目錄	IX
第一章	緒論	1
1.1 研究背景及動機	1
1.2 論文架構	3
第二章	軟硬體協同設計平台	4
2.1 DE2-70多媒體開發板	4
2.2 D5M擷取模組介紹	7
2.2.1 D5M擷取模組特性	8
2.2.2 D5M擷取模組腳位說明	10
2.2.3 D5M擷取影像格式	10
2.2.4 D5M擷取模組訊號時序圖介紹	13
2.3 4.3" LCD 觸碰面板模組介紹	15
2.3.1 LTM顯示模組特性	16
2.3.2 LTM顯示模組腳位說明	17
2.3.3 LTM顯示模組之訊號時序圖介紹	20
第三章	軟硬體協同設計方法	22
3.1 多主從系統架構介紹	22
3.2 Master端與Slave端設計介紹	25
3.2.1 Slave端設計	25
3.2.2 Master端設計	30
第四章	粒子濾波器法	34
4.1 粒子濾波器	34
4.2 競爭選取法	38
第五章	軟硬體協同設計粒子濾波器	41
5.1 粒子濾波器電路	41
5.1.1 初始化模組	42
5.1.2 權重計算主控端模組	44
5.1.3 粒子更模組	48
5.2 其他應用電路	51
5.2.1 隨機亂數模組(Random module)	51
5.2.2 FIFO暫存器	52
5.2.3 RAM	54
第六章	粒子濾波器於影像追蹤之應用	56
6.1 影像追蹤之設計架構	56
6.1.1 影像擷取	58
6.1.2 影像追蹤	59
6.1.3 影像顯示	60
6.2 實驗結果	61
6.2.1 粒子濾波器演算法實驗結果	61
6.2.2 影像擷取與顯示實驗結果	62
6.2.3 粒子濾波器用於影像追蹤	64
第七章	結論與未來研究方向	68
7.1 結論	68
7.2 未來研究方向	69
參考文獻	70
圖目錄
圖2.1 DE2開發板實體圖[26]	7
圖2.2 DE2開發板搭配數位相機與LTM顯示模組平台[26]	7
圖2.3 D5M擷取模組之實體圖[27]	8
圖2.4 RDB_D5M擷取模組之接腳連接圖[27]	10
圖2.5 D5M擷取模組影像框架[28]	11
圖2.6 CMOS擷取模組影像訊號[28]	12
圖2.7 Bayer Pattern像素圖	13
圖2.8 D5M擷取模組有效資料格式[28]	14
圖2.9 D5M擷取模組像素資料時序圖(1) [28]	14
圖2.10 D5M擷取模組像素資料時序圖(2) [28]	15
圖2.11 LTM顯示模組實體圖[29]	16
圖2.12 TRDB_LTM顯示模組之接腳連接圖[29]	18
圖2.13 LCD面板水平時序訊號說明[29]	21
圖2.14 LCD面板垂直時序訊號說明[29]	21
圖3.1傳統匯流排的傳輸方式[30]	23
圖3.2 Avalon Bus的傳輸方式[30]	23
圖3.3 Slave讀取模式時序圖[31]	27
圖3.4 Slave端寫入模式時序圖[31]	28
圖3.5多個等待週期的讀取模式[31]	29
圖3.6多個等待週期的寫入模式[31]	30
圖3.7 Master端讀取模式時序圖[31]	31
圖3.8 Master端寫入模式時序圖[31]	32
圖3.9 Master端有等待模式讀取時序圖[31]	33
圖3.10 Master端有等待模式寫入時序圖[31]	33
圖4.1粒子濾波器說明圖	37
圖4.2粒子濾波器流程圖	38
圖4.3競爭選取法說明圖	40
圖5.1粒子濾波器硬體架構圖	42
圖5.2初始化模組符號圖	42
圖5.3初始化模組架構圖	44
圖5.4權重計算主控端模組邏輯符號圖	45
圖5.5權重計算主控端與Nios II處理器之溝通	45
圖5.6權重計算主控端模組架構圖	48
圖5.7粒子更新模組邏輯符號圖	49
圖5.8粒子更新模組架構圖	51
圖5.9隨機亂數模組邏輯符號圖	52
圖5.10 FIFO模組邏輯符號圖	53
圖5.11 RAM邏輯符號圖	55
圖6.1影像追蹤系統整體架構圖	57
圖6.2影像擷取架構圖	59
圖6.3影像追蹤架構圖	60
圖6.4影像顯示架構圖	61
圖6.5即時影像追蹤實現結果展示連續圖(一)	66
圖6.6即時影像追蹤實現結果展示連續圖(二)	67
表目錄
表2.1 D5M規格參數表	9
表2.2 LTM規格參數表[29]	17
表2.3 LTM顯示模組訊號說明	19
表3.1 Slave端常用訊號表	26
表3.2 Master端常用訊號表	30
表5.1初始化模組輸出入訊號說明表	43
表5.2權重計算主控端模組輸出入訊號說明表	46
表5.3權重計算主控端模組內部暫存器說明	47
表5.4粒子更新模組輸出入訊號說明表	49
表5.5隨機亂數模組輸出入訊號說明表	52
表5.6 FIFO模組輸出入訊號說明表	54
表5.7 RAM輸出入訊號說明表	55
表6.1純軟體與軟硬體協同設計之粒子濾波器之實驗結果	62
表6.2傳統Nios II處理與多主從架構處理方式之實驗結果	63
表6.3 SDRAM與SSRAM於影像顯示效果之實驗結果	63
表6.4建模大小於影像追蹤之實驗結果	64
表6.5 PF執行位置於影像追蹤之實驗結果	65

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