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系統識別號 U0002-2207201015252400
中文論文名稱 基於SoPC之交通標誌偵測與辨識
英文論文名稱 SoPC-based Traffic Sign Detection and Recognition
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 98
學期 2
出版年 99
研究生中文姓名 陳銘燿
研究生英文姓名 Ming-Yao Chen
電子信箱 mychen0518@gmail.com
學號 697470234
學位類別 碩士
語文別 中文
口試日期 2010-07-19
論文頁數 117頁
口試委員 指導教授-易志孝
委員-周永山
委員-李世安
委員-許陳鑑
委員-簡忠漢
中文關鍵字 類神經網路  霍夫轉換  交通標誌偵測  交通標誌辨識  SoPC 
英文關鍵字 Neural Network  Hough Transform  Traffic Sign Detection  Traffic Sign Recognition  SoPC 
學科別分類 學科別應用科學電機及電子
中文摘要 本論文『基於SoPC之交通標誌偵測與辨識』之設計方式為利用多主從系統架構設計為基礎,在FPGA晶片內設計多個主控端硬體加速模組搭配Nios II處理器來實現。整個系統架構規劃為三大部份:(1)交通標誌偵測(Traffic Sign Recognition) 、(2)交通標誌辨識(Traffic Sign Recognition)及(3)動態影像擷取。主要功能為利用CMOS影像感測器偵測交通標誌,透過線上訓練類神經網路晶片(On-line Training of Neural Network Chip)將擷取之標誌分類,確定時速條件且判斷車輛是否違反標誌限制,使得修正車輛行駛方向或採取減速保持安全,避免意外事故發生。本系統擬使用軟硬體協同設計的方法,並且以較低成本開發較高級複雜演算法及較高效能的方式來設計實現駕駛輔助系統。類神經網路(Neural Network)在影像分類上有很好的表現,並且數學模型容易用硬體實現,希望突顯硬體加速器的優勢,發展出可線上學習的類神經電路,實現於Altera FPGA 開發版。如此一來,不但可以提升訓練與辨識效能,有效降低學習時間,再搭配即時動態影像,使得系統盡量滿足駕駛輔助系統在影像上的應用必須要即時(Real-Time)的特點。並且從實驗結果可以驗證所提之軟硬體共同設計確實可以用較少的影像處理時間達到即時的訓練與辨識。
英文摘要 In this thesis, an intelligent traffic sign detection and recognition system is designed and implemented on an FPGA platform based on a multiple master-slave system architecture to achieve the goals of traffic sign detection and recognition. The whole system is divided into three parts: (1) dynamic image capture, (2) traffic sign detection, and (3) traffic sign recognition. From the images captured by the CMOS image sensor, the traffic sign in the obtained image is detected through a series of image processing steps. The resultant image is further classified by a multilayer neural network with the backpropagation learning algorithm. The results of the neural network based classifier can be used to regulate the speed of car for safety and command certain actions to avoid accidents. The IDAS is realized by taking the software/hardware co-design approach which not only saves cost but also increases efficiency. To fully take advantages of hardware accelerators and satisfy the need of real-time image recognition, a very large integrated circuit (VLSI) is designed specifically for the on-line training of neural networks. Our experimental results show that hardware/software co-design approach can effectively reduce the learning time of neural networks.
論文目次 中文摘要............................................................................................................I
英文摘要...........................................................................................................II 目錄.................................................................................................................IV
圖目錄............................................................................................................VII
表目錄............................................................................................................XII
第一章 緒論............................................................................…...................1
1.1 研究動機….......................................................................................1
1.2 文獻回顧...........................................................................................2
1.3 論文章節組織...................................................................................4
第二章 影像偵測與辨識理論…..……..……..….........................…............5
2.1 背景知識...........................................................................................5
2.1.1 影像處理技術......................................................................5
2.1.2 霍夫轉換…..……………………......................................17
2.1.3 類神經網路………………………....................................21
第三章 交通標誌偵測與辨識…………....................................................41
3.1 前言……….…................................................................................41
3.2 交通標誌偵測……….....................................................................44 3.3 交通標誌辨識.................................................................................47
第四章 軟硬體協同設計平台.....................................................................51
4.1 前言.................................................................................................51
4.2 CMOS擷取模組介紹…………………………….........................55
4.2.1 CMOS擷取模組特性………..............................................55
4.2.2 CMOS擷取模組內部電路圖…..........................................58
4.2.3 CMOS擷取模組內部功能說明..........................................59
第五章 系統整合之軟硬體協同設計……….............................................67
5.1 前言.................................................................................................67
5.2 多主從系統架構介紹…….………………………........................71
5.3 Master端與Slave端設計介紹……………….….........................73
5.3.1 Slave端設計……….……...................................................74
5.3.2 Master端設計….………..…...............................................78
5.4 使用者自訂介面介紹……..……..……….……...........................82
第六章 線上學習類神經硬體加速器………….........................................88
6.1 前言……….…................................................................................88
6.2 離線訓練類神經網路.....................................................................88
6.3 線上訓練類神經網路........................................................................91
6.4 實現結果……………......................................................................105
第七章 結論與未來研究方向...................................................................110
參考文獻.......................................................................................................112
得獎經歷.......................................................................................................117

























圖目錄

圖2.1影像處理基本流程.................................................................................6
圖2.2 RGB色彩模型示意圖............................................................................8
圖2.3 Sobel演算法 與 之乘積遮罩...................................................11
圖2.4 Sobel演算法之虛乘積矩陣 .............................................................12
圖2.5 Sobel演算法之影像邊緣偵測.............................................................13
圖2.6連續高斯分佈圖形( =1.4)................................................................14
圖2.7高斯分佈之離散逼近矩陣( =1.4)....................................................15
圖2.8 Roberts 與 交叉乘積遮罩………………………….................15
圖2.9 Canny演算法之影像輪廓邊緣偵測................................................... 16
圖2.10(a)原影像空間上各點…………………….........................................19
圖2.10(b)參數空間各直線.............................................................................19
圖2.11霍夫轉換圓方程式示意圖.................................................................21
圖2.12生物神經細胞......................................................................................23
圖2.13單輸入神經元.....................................................................................25
圖2.14(a)硬極限轉移函數............................................................................ 26
圖2.14(b)單輸入hardlim神經元……….…………………………………..26
圖2.15(a)線性轉移函數…………………………………………………….26
圖2.15(b)單輸入purelin神經元……………………………………………26
圖2.16(a)Log-Sigmoid轉移函數…………………………………………...27
圖2.16(b)單輸入logsig神經元……………………………………………..27
圖2.17多輸入神經元……………………………………………………….28
圖2.18具有 個輸入的神經元簡化符號………………………………….29
圖2.19 個神經元組成的層………………………………………………..30
圖2.20由 個神經元組成的層的簡化表示……………………………….31
圖2.21三層網路的簡化表示……………………………………………….32
圖3.1駕駛輔助系統特色…………………………………………………...41
圖3.2交通標誌辨識系統流程……………………………………………...42
圖3.3速限交通標誌………………………………………………………...43
圖3.4系統規劃圖…………………………………………………………...44
圖3.5交通標誌偵測概念圖………………………………………………...44
圖3.6軟體端模擬流程圖…………………………………………………...45
圖3.7軟體端模擬步驟二示意圖………………………………………...…46
圖3.8軟體端模擬步驟三示意圖………………….………………………..47
圖3.9類神經網路辨識示意圖……………………………………………...48
圖3.10類神經網路訓練收斂圖…………………………………………….50
圖4.1DE2開發板實體圖……………………………………….…………...54
圖4.2DE2開發板搭配DVD播放器與LCM顯示模組平台……………...54
圖4.3DE2開發板搭配數位相機與LCM顯示模組平台……….………….54
圖4.4CMOS擷取模組之實體圖…………….……………………………...55
圖4.5CMOS擷取模組之接腳訊號圖……………….……………………...58
圖4.6 CMOS擷取模組內部功能方塊...........................................................59
圖4.7CMOS擷取模組影像框架...................................................................60
圖4.8CMOS擷取模組有效資料格式............................................................61
圖4.9CMOS擷取模組影像訊號....................................................................62
圖4.10Bayer Pattern像素...............................................................................63
圖4.11CMOS擷取模組像素資料時序圖(1).................................................63
圖4.12CMOS擷取模組像素資料時序圖(2).................................................64
圖4.13 界面16位讀出順序......................................................................65
圖4.14 界面16位寫入順序......................................................................66
圖5.1傳統的軟硬體共同設計流程...............................................................68
圖5.2 SoPC系統的軟硬體共同設計架.........................................................69
圖5.3 Nios II處理器標準硬體週邊功能方塊圖...........................................70
圖5.4傳統匯流排的傳輸方式.......................................................................71
圖5.5 Avalon Bus的傳輸方式........................................................................71
圖5.6 Slave讀取模式時序圖.........................................................................75
圖5.7 Slave端寫入模式時序圖.....................................................................76
圖5.8多個等待週期的讀取模式...................................................................77
圖5.9多個等待週期的寫入模式...................................................................77
圖5.10 Master端讀取模式時序圖.................................................................79
圖5.11 Master端寫入模式時序圖.................................................................79
圖5.12 Maste端有等待模式讀取時序圖......................................................81
圖5.13 Master端有等待模式寫入時序圖.....................................................81
圖5.14整合使用者自定介面至Avalon Bus內示意圖.................................84
圖5.15 SoPC Builder使用者介面..................................................................84
圖5.16新增使用者自訂介面程式.................................................................85
圖5.17連接使用者自訂介面訊號.................................................................85
圖5.18 Component Editor介面......................................................................86
圖5.19 Avalon Bus 連接圖............................................................................87
圖6.1多輸入神經元數學模型…………………………….………..............90
圖6.2多輸入神經元硬體模型.......................................................................90
圖6.3硬體訓練流程圖...................................................................................92
圖6.4XOR問題學習收斂圖...........................................................................94
圖6.5初始化硬體方塊圖...............................................................................95
圖6.6 (a)前向傳遞硬體方塊圖......................................................................97
圖6.6 (b)前向傳遞硬體方塊圖......................................................................97
圖6.7靈敏度倒傳遞硬體方塊圖...................................................................99
圖6.8動量方法硬體方塊圖.........................................................................100
圖6.9(a)驗証步伐硬體方塊圖.....................................................................102
圖6.9(b)驗証步伐硬體方塊圖.....................................................................102
圖6.10更新步驟硬體方塊圖.......................................................................104
圖6.11 Master_initial_Weight模組符號圖..................................................105
圖6.12 Master_initial_Weight實際訊號圖..................................................106
圖6.13為Master_Weight_Reader_First模組符號圖..................................106
圖6.14為Master_Weight_Reader_First實際訊號圖...................................107
圖6.15為Master_Weight_Reader_Second模組符號圖..............................108
圖6.16為Master_Weight_Reader_Second實際訊號圖..............................108



表目錄

表3.1類神經網路訓練參數表.......................................................................49
表5.1 Slave端常用訊號表.............................................................................74
表5.2 Master端常用訊號表...........................................................................78
表6.1資料表示法參數表...............................................................................91
表6.2類神經網路訓練參數表.......................................................................93
表6.3軟體模擬與硬體加速比較表.............................................................109
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