此篇論文主要在陳述一種新的維特比解碼器的架構，目的在提高原有IS-95, IS-2000, 8021.x 的傳輸率。因原本既有的標準，都是使用較高的輸入頻率來達成標準內的傳輸率，或者使用較低的輸入頻率，再用內部的PLL，提供出較高的觸發頻率給內部的維特比解碼器來達成。但是在新的802.11x標準內，已將輸入觸發頻率與傳輸率，幾乎相等，如802.11a/b/g或將出爐的802.11、802.16a。但這些標準都必須使用到維特比解碼器。為了這些標準，此篇論文提供一種新的架構，不需要PLL，也不需較高的觸發頻率，既可達到新標準的傳輸率。
就原IS-95標準，其輸入頻率為10MHZ，-而其傳輸率為1.22Mbps，如果使用此架構，可將其傳輸率提升至40Mbps，其改善倍率將近32倍。如果以IS-2000為比較 (3.1Mbps)，此架構的改善倍率，亦可達到12倍之多。而如果以現存的802.11 a/b/g，可將其原有的輸入觸發頻率40MHZ降至10MHZ，其輸傳輸率仍可維持在27Mbps，甚至達到40Mbps。並且在未來的802.11n標準下，其傳輸率必須達到100Mbps，如輸入頻率維持在40MHZ，此架構可提供到160Mbps傳輸率，仍然遠超過802.11n的標準。而且於生還者路徑(Trace Back Unit)的單元中，也將可大幅減少其所佔積體電路的面積。

This thesis describes a new structure of the Viterbi Decoder for IS-95, IS-2000, 802.11x. Originally, higher input trigger frequency or lower input frequency for Viterbi Decoder were used to meet the transitions requirements. Nowadays, input trigger frequency almost equals to the transmitting rate in new 802.11x standard, such as 802.11a/b/g,802.11n,and 802.16a .This new VD structure does not need PLL, nor rising input trigger frequency to meet the transmission rate of the new standard.
Original IS-95 standard, its inputs trigger frequency is 10MHZ, but the general transmission rate is 1.22Mbps. If we use this structure, the transmit rate will be improved to 40Mbps, nearly 32 times faster than the original as well as IS-2000 standard (3.1Mbps), it improves nearly 12 times. Moreover, as for existing 40MHZ 802.11 a/b/g input trigger frequency, it can be done by 10MHz resulting 27Mbps transmitting rate. For future 802.11n standard, when transmitting rate must reach 100Mbps, its input trigger frequency can still be kept at 40MHZ. This input trigger frequency can even offer a transmitting rate up to 160Mbps for the 802.11n standard. As the result, the decoder has achieved a higher decoding rate without any degradation in performance. One result also shows it can reduce the area accounted for the integrated circuit by a wide margin

第一章:緒論	1
1.1 前言	1
1.2 研究動機	3
1.3 論文架構	4
第二章:遞迴碼與維特比解碼器的原理及架構	5
2.1 引言	5
2.2 遞迴編碼器	6
2.3 維特比解碼器演算法	10
第三章:高傳輸率維特比解碼器	17
3.1 高速的ACSU&FBU	17
3.2 小記憶體空間的SMU	21
3.3 高傳輸率的解碼器	25
第四章:高傳輸維特比解碼器的實現與分析	29
4.1 基本模擬方塊	29
4.2 高傳輸率模擬	33
4.3 維特比解碼器的消耗功率及面積分析	36
4.4 維特比解碼器的錯誤修正能力	39
第五章:結論及未來展望	42
參考文獻	43



圖目
圖 1.1: 802.11G BASEBAND功能	3
圖2.2: 遞迴編碼器狀態表	7
圖2.3: 遞迴編碼器狀態圖	8
圖 2.4: (2，1，2)遞迴編碼的格子圖形	9
圖 2.5: 編碼&解碼	10
圖 2.6: 維特比解碼器格子圖形	11
圖 2.7: 維特比解碼器的追溯路徑	12
圖 2.8: 維特比解碼器的基本的方塊	14
圖 2.9: 遞迴碼的格子圖型	15
圖 2.10: ACSU硬體架構	15
圖 3.1: G0 = 1338(10110112), G1=1718(11110012),遞迴碼編碼器架構	18
圖 3.2: 遞迴碼的先進先出暫存器	18
圖 3.3: 漢明距離暫存器	19
圖 3.4: ACS單位的先進先出暫存器的架構	20
圖 3.5: 維特比解碼器架構處理程序	21
圖 3.6: (2，1，2)格子圖示	22
圖 3.7: 生還者追蹤路徑處理程序	23
圖 3.8: SMU的儲存內容	23
圖 3.9: TBU追溯程序	24
圖 3.10: 向左移N個深度	26
圖 3.11: SMU的記憶體架構	26
圖 3.12: 2T TRACE BACK	27
圖 4.1: 程式架構與流程	29
圖 4.2: RESET,INITIAL AND BGU	31
圖 4.3: BMU & ACSU	32
圖 4.4: TBU	33
圖 4.5: 1-步之ACSU 和 TBU	34
圖 4.6: 2-步之ACSU 和 TBU	34
圖 4.7: 3-步之ACSU 和 TBU	35
圖 4.8: 4-步之ACSU 和 TBU	35
圖 4.9: 擁有通道模型的程式架構與流程	39
圖 4.10: 輸入四位元干擾一位元的錯誤修正	40
圖 4.11: 輸入四位元干擾兩位元的錯誤修正	41
 
表目
表 4.1: SMU&TBU(2,1,2)比較表	37
表 4.2: 維特比解碼器(2,1,2)比較表	37
表 4.3: SMU&TBU(2,1,6)比較表	37
表 4.4: 維特比解碼器(2,1,6)比較表	38

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