在本論文中，我們提出了一個十位元五十百萬赫茲的導管式類比數位轉換器，並利用其較寬的頻帶可應用在IEEE 802.11 a 無線通訊系統或數位電視上。在整體的架構上採用的是每階段實現1.5 位元並結合數位錯誤修正技術來達到所需要的規格。所提出的導管式類比數位轉換器的微分非線性誤差(DNL)和積分非線性誤差(INL)分別在± 0.45 LSB和± 0.46 LSB的範圍內。在取樣頻率為五十百萬赫茲、輸入頻率為五百萬赫茲和雙端輸入電壓範圍為0.65伏特~1.85伏特時經過Hspice所模擬的訊號雜訊動態比(SNDR)為60.5dB而有效位元(effective number of bits)則為十位元。當供應電壓為2.5伏特、取樣頻率為五十百萬赫茲時，對於所有電路所測量到的功率消耗為93mW，此研究所提出的導管式類比數位轉換器在0.35微米2P4M標準互補式金氧半製程下完成並交送給國家晶片中心完成下線，整個晶片的面積不含PADs為2.8×1.5 mm2。

In this paper, a 10-bit 50MSample/s Nyquist-rate CMOS pipelined analog-to-digital converter (ADC) with digital correction is presented for the IEEE 802.11a WLAN and HDTV applications. The digital correction technique adapted by this pipelined ADC can give more accurate demands in application. The simulated  DNL and INL of the presented pipelined A/D converter are suppressed within ± 0.45 LSB and ± 0.46 LSB, respectively. The simulated SNDR is 60.5dB and the effective number of bits is 10 at the rate of 50MSample/s with a 5MHz input frequency. This presented circuit has been fabricated in a 0.35um 2P4M CMOS process. The dissipation power of 93mW in this ADC was measured under the sampling rate of 50MHz at 2.5V supply voltage. And its core area without PADs is 2.8×1.5 mm2.

Chapter 1 Introduction....................................1
1.1 Motivations...........................................1
1.2 Organizations.........................................2
Chapter 2	Fundamentals of the pipelined A/D Converter......3
2.1 Introduction..........................................3
2.2 ADC Performance Metrics...............................3
2.2.1 Resolution..........................................3
2.2.2 Signal to Noise Ratio...............................5
2.2.3 Signal to Noise Distortion Ratio....................7
2.2.4 Dynamic Range.......................................8
2.2.5 Nonlinearity........................................9
2.3 Classification.......................................11
2.4 Review of Nyquist Rate ADC Architecture..............13
2.4.1 Flash ADC..........................................13
2.4.2 Two-Step ADC.......................................15
2.4.3 Pipelined ADC......................................17
Chapter 3	Design of the Pipelined ADC.....................18
3.1 Introduction.........................................18
3.2 Principles of the pipelined ADC......................18
3.2.1 Digital Error Correction...........................21
3.2.2 A 1.5-bit/stage pipelined..........................24
3.3 Accuracy Consideration...............................26
3.3.1 Switch on Resistance...............................26
3.3.2 Charge Injection...................................29
3.3.3 Clock Feedthrough..................................32
Chapter 4	Circuits Design and Implement...................33
4.1 Sample and Hold......................................33
4.1.1 Gain-Boosted Folded-Cascode Amplifier..............34
4.1.2 Common Mode Feedback Circuit.......................37
4.1.3 Clock Bootstrapped Switch..........................38
4.2 1.5-bit Stage........................................39
4.2.1 1.5-bit sub-ADC....................................41
4.2.2 Comparator.........................................42
4.2.3 Multiplying Digital-Analog Converter...............43
4.3 Clock Generator......................................44
4.4 Delay Cell and Adder.................................46
Chapter 5	Simulation and Experimental Results.............47
5.1 Simulation Results...................................47
5.1.1 Simulation Results of the OPAMP....................47
5.1.2 Simulation Results of the S/H......................49
5.1.3 Simulation Results of the Comparator...............50
5.1.4 Simulation Results of the 1.5-bit sub-ADC..........52
5.1.5 Simulation Results of the Pipelined ADC............52
5.1.6 SNDR of the Pipelined ADC..........................54
5.1.7 DNL and INL of the Pipelined ADC...................54
5.2 Layout and Die Photo.................................55
5.3 Test Considerations..................................56
5.4 Measurement Results..................................59
Chapter 6	 Conclusions....................................60
6.1 Conclusions..........................................60
6.2 Future Work..........................................62
Reference................................................63

Figure 1.1 ADCs used in DSP applications..................2
Figure 2.1 Input vs. output of an ADC.....................4
Figure 2.2 (a) Input/output transfer diagram (b) Quantization error of the ADC.............................5
Figure 2.3 The probability density function of the error signal....................................................6
Figure 2.4 The definition of dynamic range................9
Figure 2.5 Error sources (a) Offset error (b) Gain error
(c) Linearity error (d) Missing code.....................10
Figure 2.6 Transfer characteristic with nonlinearity.....11
Figure 2.7 Resolution and speed for each ADCs............13
Figure 2.8 Flash ADC.....................................15
Figure 2.9 Two-step ADC..................................16
Figure 2.10 Pipelined ADC structure......................17
Figure 3.1 Block diagram of 2-bit/stage..................19
Figure 3.2 Signal conversion of a 8-bit pipelined ADC....19
Figure 3.3 The transfer curve of one stage...............20
Figure 3.4 The residue plot..............................21
Figure 3.5 The residue plot (a) sub-ADC errors (b) sub-DAC errors...................................................23
Figure 3.6 Analog residue with digital error correction..23
Figure 3.7 The pipelined ADC structure...................25
Figure 3.8 Timing of generated codes.....................26
Figure 3.9 (a) S/H circuit (b) Equivalent circuit........28
Figure 3.10 On-resistance of the COMS....................29
Figure 3.11 Charge injection when a switch turns off.....29
Figure 3.12 Dummy device to reduce charge injection......30
Figure 3.13 Complementary switches to reduce charge injection................................................31
Figure 3.14 Differential sampling circuit................31
Figure 3.15 Clock Feedthrough in a sampling circuit......32
Figure 4.1 Sample and hold...............................34
Figure 4.2 Gain-boosted folded-cascode amplifier.........36
Figure 4.3 Common mode feedback circuit..................37
Figure 4.4 Bootstrapped switch...........................38
Figure 4.5 1.5-bit stage architecture....................40
Figure 4.6 1.5-bit sub-ADC architecture..................41
Figure 4.7 Comparator....................................42
Figure 4.8 Multiplying digital to analog converter.......43
Figure 4.9 Clock Generator...............................44
Figure 4.10 Timing of nonoverlap clock...................44
Figure 4.11 The delay cell...............................45
Figure 4.12 Adder for digital error correction...........46
Figure 5.1 The output swing of the opamp.................48
Figure 5.2 AC response of the opamp......................48
Figure 5.3 The simulation result of the slew rate........49
Figure 5.4 The output and input curve of the S/H.........50
Figure 5.5 Simulation of the comparator..................51
Figure 5.6 Simulation of the comparator with SR-latch....51
Figure 5.7 Simulation of the 1.5-bit sub-ADC.............52
Figure 5.8 Simulation of the pipelined ADC...............53
Figure 5.9 Simulation of the converted back digital codes....................................................53
Figure 5.10 Simulation of the FFT........................54
Figure 5.11 (a) DNL (b) INL..............................55
Figure 5.12 The layout of the pipelined ADC with PADs....55
Figure 5.13 The die photo of the pipelined ADC...........56
Figure 5.14 Test setup...................................57
Figure 5.15 (a) LM317 regulator (b) Bypass filter at regulator output.........................................57
Figure 5.16 AC coupled circuit...........................58
Figure 5.17 (a) AWG420 Arbitrary Waveform (b) TLA5201 Logic Analyzer...........................................58
Figure 5.18 PCB board of th pipelined ADC................59
Figure 5.19 Measurement result of the pipelined ADC......59

Table 2.1 Classifications of ADCs .......................12
Table 3.1	Comparison of original coding and Modified coding with digital error correction........................... 24
Table 5.1	Specifications of the opamp.....................49
Table 6.1	Performance Summary.............................60
Table 6.2	Performance comparisons with other literatures..61

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