淡江大學覺生紀念圖書館 (TKU Library)
進階搜尋


下載電子全文限經由淡江IP使用) 
系統識別號 U0002-2206200511255900
中文論文名稱 實現十位元五十百萬赫茲之導管式類比數位轉換器
英文論文名稱 A 10-bit 50MSample/s Pipelined Analog-to-Digital Converter
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 93
學期 2
出版年 94
研究生中文姓名 黃世麟
研究生英文姓名 Shih-Lin Huang
學號 692390452
學位類別 碩士
語文別 英文
口試日期 2005-06-09
論文頁數 65頁
口試委員 指導教授-郭建宏
委員-黃育賢
委員-陳建中
委員-陳淳杰
委員-江正雄
中文關鍵字 類比數位轉換  導管式  取樣與保持 
英文關鍵字 Analog-to-Digital(A/D)  Pipelined  sample-and-hold 
學科別分類 學科別應用科學電機及電子
中文摘要 在本論文中,我們提出了一個十位元五十百萬赫茲的導管式類比數位轉換器,並利用其較寬的頻帶可應用在IEEE 802.11 a 無線通訊系統或數位電視上。在整體的架構上採用的是每階段實現1.5 位元並結合數位錯誤修正技術來達到所需要的規格。所提出的導管式類比數位轉換器的微分非線性誤差(DNL)和積分非線性誤差(INL)分別在± 0.45 LSB和± 0.46 LSB的範圍內。在取樣頻率為五十百萬赫茲、輸入頻率為五百萬赫茲和雙端輸入電壓範圍為0.65伏特~1.85伏特時經過Hspice所模擬的訊號雜訊動態比(SNDR)為60.5dB而有效位元(effective number of bits)則為十位元。當供應電壓為2.5伏特、取樣頻率為五十百萬赫茲時,對於所有電路所測量到的功率消耗為93mW,此研究所提出的導管式類比數位轉換器在0.35微米2P4M標準互補式金氧半製程下完成並交送給國家晶片中心完成下線,整個晶片的面積不含PADs為2.8×1.5 mm2。
英文摘要 In this paper, a 10-bit 50MSample/s Nyquist-rate CMOS pipelined analog-to-digital converter (ADC) with digital correction is presented for the IEEE 802.11a WLAN and HDTV applications. The digital correction technique adapted by this pipelined ADC can give more accurate demands in application. The simulated DNL and INL of the presented pipelined A/D converter are suppressed within ± 0.45 LSB and ± 0.46 LSB, respectively. The simulated SNDR is 60.5dB and the effective number of bits is 10 at the rate of 50MSample/s with a 5MHz input frequency. This presented circuit has been fabricated in a 0.35um 2P4M CMOS process. The dissipation power of 93mW in this ADC was measured under the sampling rate of 50MHz at 2.5V supply voltage. And its core area without PADs is 2.8×1.5 mm2.
論文目次 Chapter 1 Introduction....................................1
1.1 Motivations...........................................1
1.2 Organizations.........................................2
Chapter 2 Fundamentals of the pipelined A/D Converter......3
2.1 Introduction..........................................3
2.2 ADC Performance Metrics...............................3
2.2.1 Resolution..........................................3
2.2.2 Signal to Noise Ratio...............................5
2.2.3 Signal to Noise Distortion Ratio....................7
2.2.4 Dynamic Range.......................................8
2.2.5 Nonlinearity........................................9
2.3 Classification.......................................11
2.4 Review of Nyquist Rate ADC Architecture..............13
2.4.1 Flash ADC..........................................13
2.4.2 Two-Step ADC.......................................15
2.4.3 Pipelined ADC......................................17
Chapter 3 Design of the Pipelined ADC.....................18
3.1 Introduction.........................................18
3.2 Principles of the pipelined ADC......................18
3.2.1 Digital Error Correction...........................21
3.2.2 A 1.5-bit/stage pipelined..........................24
3.3 Accuracy Consideration...............................26
3.3.1 Switch on Resistance...............................26
3.3.2 Charge Injection...................................29
3.3.3 Clock Feedthrough..................................32
Chapter 4 Circuits Design and Implement...................33
4.1 Sample and Hold......................................33
4.1.1 Gain-Boosted Folded-Cascode Amplifier..............34
4.1.2 Common Mode Feedback Circuit.......................37
4.1.3 Clock Bootstrapped Switch..........................38
4.2 1.5-bit Stage........................................39
4.2.1 1.5-bit sub-ADC....................................41
4.2.2 Comparator.........................................42
4.2.3 Multiplying Digital-Analog Converter...............43
4.3 Clock Generator......................................44
4.4 Delay Cell and Adder.................................46
Chapter 5 Simulation and Experimental Results.............47
5.1 Simulation Results...................................47
5.1.1 Simulation Results of the OPAMP....................47
5.1.2 Simulation Results of the S/H......................49
5.1.3 Simulation Results of the Comparator...............50
5.1.4 Simulation Results of the 1.5-bit sub-ADC..........52
5.1.5 Simulation Results of the Pipelined ADC............52
5.1.6 SNDR of the Pipelined ADC..........................54
5.1.7 DNL and INL of the Pipelined ADC...................54
5.2 Layout and Die Photo.................................55
5.3 Test Considerations..................................56
5.4 Measurement Results..................................59
Chapter 6 Conclusions....................................60
6.1 Conclusions..........................................60
6.2 Future Work..........................................62
Reference................................................63

Figure 1.1 ADCs used in DSP applications..................2
Figure 2.1 Input vs. output of an ADC.....................4
Figure 2.2 (a) Input/output transfer diagram (b) Quantization error of the ADC.............................5
Figure 2.3 The probability density function of the error signal....................................................6
Figure 2.4 The definition of dynamic range................9
Figure 2.5 Error sources (a) Offset error (b) Gain error
(c) Linearity error (d) Missing code.....................10
Figure 2.6 Transfer characteristic with nonlinearity.....11
Figure 2.7 Resolution and speed for each ADCs............13
Figure 2.8 Flash ADC.....................................15
Figure 2.9 Two-step ADC..................................16
Figure 2.10 Pipelined ADC structure......................17
Figure 3.1 Block diagram of 2-bit/stage..................19
Figure 3.2 Signal conversion of a 8-bit pipelined ADC....19
Figure 3.3 The transfer curve of one stage...............20
Figure 3.4 The residue plot..............................21
Figure 3.5 The residue plot (a) sub-ADC errors (b) sub-DAC errors...................................................23
Figure 3.6 Analog residue with digital error correction..23
Figure 3.7 The pipelined ADC structure...................25
Figure 3.8 Timing of generated codes.....................26
Figure 3.9 (a) S/H circuit (b) Equivalent circuit........28
Figure 3.10 On-resistance of the COMS....................29
Figure 3.11 Charge injection when a switch turns off.....29
Figure 3.12 Dummy device to reduce charge injection......30
Figure 3.13 Complementary switches to reduce charge injection................................................31
Figure 3.14 Differential sampling circuit................31
Figure 3.15 Clock Feedthrough in a sampling circuit......32
Figure 4.1 Sample and hold...............................34
Figure 4.2 Gain-boosted folded-cascode amplifier.........36
Figure 4.3 Common mode feedback circuit..................37
Figure 4.4 Bootstrapped switch...........................38
Figure 4.5 1.5-bit stage architecture....................40
Figure 4.6 1.5-bit sub-ADC architecture..................41
Figure 4.7 Comparator....................................42
Figure 4.8 Multiplying digital to analog converter.......43
Figure 4.9 Clock Generator...............................44
Figure 4.10 Timing of nonoverlap clock...................44
Figure 4.11 The delay cell...............................45
Figure 4.12 Adder for digital error correction...........46
Figure 5.1 The output swing of the opamp.................48
Figure 5.2 AC response of the opamp......................48
Figure 5.3 The simulation result of the slew rate........49
Figure 5.4 The output and input curve of the S/H.........50
Figure 5.5 Simulation of the comparator..................51
Figure 5.6 Simulation of the comparator with SR-latch....51
Figure 5.7 Simulation of the 1.5-bit sub-ADC.............52
Figure 5.8 Simulation of the pipelined ADC...............53
Figure 5.9 Simulation of the converted back digital codes....................................................53
Figure 5.10 Simulation of the FFT........................54
Figure 5.11 (a) DNL (b) INL..............................55
Figure 5.12 The layout of the pipelined ADC with PADs....55
Figure 5.13 The die photo of the pipelined ADC...........56
Figure 5.14 Test setup...................................57
Figure 5.15 (a) LM317 regulator (b) Bypass filter at regulator output.........................................57
Figure 5.16 AC coupled circuit...........................58
Figure 5.17 (a) AWG420 Arbitrary Waveform (b) TLA5201 Logic Analyzer...........................................58
Figure 5.18 PCB board of th pipelined ADC................59
Figure 5.19 Measurement result of the pipelined ADC......59

Table 2.1 Classifications of ADCs .......................12
Table 3.1 Comparison of original coding and Modified coding with digital error correction........................... 24
Table 5.1 Specifications of the opamp.....................49
Table 6.1 Performance Summary.............................60
Table 6.2 Performance comparisons with other literatures..61





參考文獻 [1] Yotsuyanagi, T. Etoh, and K. Hirara, “A 10 b 50 MHz pipelined CMOS A/D converter with S/H,” Solid-State Circuits, IEEE Journal of, Vol. 28, Issue: 3, pp. 292–300, Mar 1993.
[2] J. Arias, V. Boccuzzi, L. Quintanilla, L. Enriquez, D. Bisbal, M. Banu, and J. Barbolla, “Low-power pipeline ADC for wireless LANs,” Solid-State Circuits, IEEE Journal of, Vol. 39, Issue: 8, pp. 1338–1340, Aug. 2004.
[3] K. W. Cheng, A 1.0-V, 10-Bit COMS Pipelined Analog-to-Digital Converter, Master’s Program in Electrical Engineering, National Taiwan University, June 2002.
[4] R. J. Baker, CMOS Mixed-Signal Circuit Design, IEEE press, 2003..
[5] C. G. Cheng, Design of a 10-bit pipelined Analog-to-Digital Converter for parallel structure, Master’s Program in Electrical Engineering, National Taiwan Ocean University, June 2002.
[6] C. M. Cheng, Design of a 10-bit 50MHz pipelined Analog-to-Digital Converter, Master’s Program in Electrical Engineering, Tamkang University, June, 2003.
[7] K. Balasubramanian, “A flash ADC with reduced complexity,” Industrial Electronics, IEEE Transactions on Volume 42, Issue 1, pp. 106-108, Feb. 1995.
[8] Yotsuyanagi, T. Etoh, and K. Hirara, “A 10 b 50 MHz pipelined CMOS A/D converter with S/H,” Solid-State Cir cuits, IEEE Journal of, Vol. 28, Issue: 3, pp. 292–300, Mar 1993.
[9] D. A. Johns, K. Martin, ”Analog Integrated Circuit design,” 1997.
[10] M. Ishikawa, T. Tsukahara, “An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H,” Solid-State Circuits, IEEE Journal of, Vol. 24, Issue: 6, pp. 1485–1491, Dec. 1989.
[11] T. H. Kuo, K. D. Chen, H. R. Yeng,” A wideband CMOS sigma-delta modulator with incremental data weighted averaging,” Solid-State Circuits, IEEE Journal of Vol. 37, Issue 1, pp. 11–17, Jan. 2002.
[12] C. H. Kuo, The Designand Implementation of Low Voltage CMOS D elta Sigma Modulator, Ph.D. thesis, Department of Electrical Engineering, National Taiwan Univ ersity,June, 2003.
[13] D. G. Nairn, A. S. Sedra, “A 10-bit, 3 V, 100 MS/s pipelined ADC,” Custom Integrated Circuits Conferenc, Proceedings of the IEEE, pp. 257–260, May 2000.
[14] C. Yun, P. R. Gray, B. Nikolic, “A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR,” Solid-State Circuits, IEEE Journal of Vol. 39, Issue 12, pp. 2139–2151, Dec. 2004.
[15] M. Das, “Improved design criteria of gain-boosted CMOS OTA with high-speed optimizations,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] Vol. 49, Issue 3, pp. 204–207, March 2002.
[16] Y. D. Jeon, B. L. Jeon, S. C. Lee, S. M. Yoo, “A 12b 50 MHz 3.3 V CMOS Acquisition Time Minimized A/D Converter,” Design Automation Conference, Proceedings of the ASP-DAC 2000. Asia and South Pacific, 25-28 pp. 613–616, Jan. 2000.
[17] J. B. Hughes, M. Mec, W. Donaldson, “A low voltage 8-bit, 40 MS/s switched-current pipeline analog-to-digital converter,” Circuits and Systems, ISCAS 2001. The 2001 IEEE International Symposium on Vol. 1, pp. 572 - 575, May 2001.
[18] L. H, M. Hassoun, “A 9-b 40-MSample/s reconfigurable pipeline analog-to-digital converter,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on]
Vol. 49, Issue 7, pp. 449 – 456, July 2002.
[19] P. Hui, M. Segami, M. Choi, C. Ling, A. A. Abidi, “A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR,” Solid-State Circuits, IEEE Journal of Vol. 35, Issue 12, pp. 1769–1780, Dec. 2000.
[20] M. Yotsuyanagi, T. Etoh, L. Hirata,” A 10 b 50 MHz pipelined CMOS A/D converter with S/H,” Solid-State Circuits, IEEE Journal of Vol. 28, Issue 3, pp. 292–300, March 1993.
[21] X. Wang, P. J. Hurst, S. H. Lewis,” A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration,” Solid-State Circuits, IEEE Journal of Vol. 39, Issue 11, pp.1799–1808, Nov. 2004.
[22] J. Li, U. K. Moon,” A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique,” Solid-State Circuits, IEEE Journal of Vol. 39, Issue 9, pp.1468–1476, Sept. 2004.
[23] B. Murmann, B. E. Boser,” A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” Solid-State Circuits, IEEE Journal of Vol. 38, Issue 12, pp. 2040–2050, Dec. 2003.
[24] M. J. Choe, B. S. Song, K. Bacrania,” A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming,” Solid-State Circuits, IEEE Journal of Vo. 35, Issue 12, pp. 1781-1790,Dec.2000.
[25] S. Sonkusale, J. Spiegel, K. Nagaraj,” True background calibration technique for pipelined ADC,” Electronics Letters, Vol. 36, Issue 9, pp. 786-788, April 2000.



論文使用權限
  • 同意紙本無償授權給館內讀者為學術之目的重製使用,於2008-07-14公開。
  • 同意授權瀏覽/列印電子全文服務,於2008-07-14起公開。


  • 若您有任何疑問,請與我們聯絡!
    圖書館: 請來電 (02)2621-5656 轉 2281 或 來信