本論文在基於低功率消耗的概念下，降低輸入電壓變為首要工作。在0.18um製程下，輸入電壓為1.8V為基本，如何降低到1V以下系統還能正常運作便是研究中的一個重要議題。低壓降線性穩壓器運用於提供穩定電壓，輸出電壓的精準度極為重要，線性調節率與負載調節率便為精準度的參考指標。
    因此，整體電路可分為三部分，第一部分為利用漸進式移位暫存控制器產生數位訊號來開啟功率電晶體以達到輸出電壓，第二部分便以移位暫存器來細微調整輸出電壓的大小，以求精準度，第三部分為比較器。在負載電流的限制下，功率電晶體的大小便為重要，在此利用8 bit的移位暫存控制器來驅使足夠大的電晶體以求達到理想的輸出電壓，由於此時輸出電壓僅為接近輸出電壓，並未達到極為準確，因此加入80級的移位暫存器來控制尺寸極小的功率電晶體，此微調範圍可包含於TT、FF、SS三種製程，使得規格都有符合預期之規格。
    透過上述的電路設計加以模擬驗證可得到一輸入電壓低於1V之無輸出電容數位式低壓降線性穩壓器，輸入電壓為0.7V，輸出電壓為0.5V。最大負載電流為20mA，與精準度有關的負載調節率可達到0.1mV/mA，而靜態電流卻僅為2.5uA。

In this thesis, the concept based on low power consumption, and reducing the input voltage is become the top priority. In 0.18um process, the input voltage of 1.8V to basic, how to reduce to less 1V is an important topic in the study of normal operation. Low dropout regulator should be applied to provide a stable voltage, and the accuracy of output voltage is extremely important. So the line regulation and the load regulation will be the accuracy of the reference indicators.
    Therefore, the overall circuit can be divided into three parts. The first part is using SAR_Control digital signal to turn on the power transistor for achieving the output voltage. The second part is using shift register to fine tuning output voltage in order to accuracy. The third part is comparator. The size of power transistor will be important because the limit of the load current. Using 8 bit SAR_Control to drive transistor large enough for achieving the desired output voltage. The output voltage only close to the desired voltage, and it does not meet the extremely accurate. So adding 80 bit shift register to control the small size power transistor. The fine tuning range can be included in the TT,FF,SS, three kind of process, and can be meet the expected specifications.
    Though the above mentioned circuit design and simulation can be obtained a sub-1V Output-Capacitor-Free Digitally Controlled LDO. The input voltage is 0.7V, and output voltage is 0.5V. When the heavy load current is 20mA, the line regulation is 0.1mV / mA, and the quiescent is only 2.5uA.

目錄
中文摘要	I
英文摘要	II
內文目錄	V
圖表目錄	VII

第一章  緒論	1
1.1 研究背景與動機	1
1.2 設計流程	2
1.3 論文架構	4

第二章  低壓降線性穩壓器	5
2.1低壓降線性穩壓器概論	5
2.2低壓降線性穩壓器之特性參數	7
2.2.1輸出電壓差	7
2.2.2靜態電流	8
2.2.3線性調節率	9
2.2.4負載調節率	10
2.2.5電源效率	12
2.2.6輸出準確率	12

2.3穩定性分析	14
2.3.1暫態響應	19
2.3.2頻率響應	21
2.4文獻回顧與探討	25
2.4.1具超級源極隨耦器之低壓降線性穩壓器	25
2.4.2無輸出電容應用於SoC之低壓降線性穩壓器	26
2.4.3具高效率低靜態電流之數位式低壓降線性穩壓器	27
2.4.4具PLL調整、快速DVS電源管理之數位式低壓降線性穩壓器	28

第三章  可調式輸出電壓之低壓降線性穩壓器設計	30
3.1低壓降線性穩壓器設計	30
3.1.1漸進式移位暫存控制器	31
3.1.2移位暫存器	33
3.1.3反相器	37
3.1.4 PMOS電源陣列	38
3.2電路模擬與佈局	39
3.3量測考量與結果	66

第四章  結論	71
4.1結論與未來展望	71

參考文獻	72
圖目錄

圖1.1晶片設計流程圖	3
圖2.1傳統低壓降線性穩壓器之電路圖	5
圖2.2低壓降線性穩壓器之輸出/入電壓曲線圖	8
圖2.3靜態電流示意圖	9
圖2.4低壓降線性穩壓器之線性調節率示意圖	10
圖2.5低壓降線性穩壓器負載調節率示意圖	11
圖2.6輸出電壓誤差示意圖	12
圖2.7誤差放大器偏移示意圖	14
圖2.8電阻值誤差示意圖	14
圖2.9 PMOS功率電晶體的低壓降線性穩壓器	16
圖2.10 NMOS功率電晶體的低壓降線性穩壓器	16
圖2.11應用於SoC內的補償方式	17
圖2.12利用DFC電路調整相位邊限	18
圖2.13低壓降線性穩壓器及其輸出電容與負載電流	19
圖2.14低壓降線性穩壓器輸出電壓對負載電流之反應圖	19
圖2.15低壓降線性穩壓器之交流分析等效模型	21
圖2.16等效串聯電阻過大與過小的情況	23
圖2.17輕、重載與ESR補償	24
圖2.18低靜態電流超級源極隨耦器之LDO電路	25
圖2.19無輸出電容應用於SoC之LDO電路	26
圖2.20具高效率低靜態電流之數位式低壓降線性穩壓器	27
圖2.21具有PLL調整、快速DVS電源管理之架構圖	28
圖3.1無輸出電容之數位式低壓降線性穩壓器	30
圖3.2八位元的漸進式移位暫存控制器電路圖	31
圖3.3第k個多輸入移位暫存器與真值表	32
圖3.4解碼器與多工器電路圖	32
圖3.5 3-bit二元搜尋演算法流程圖	33
圖3.6右移暫存器	34
圖3.7四位元串列輸入、串列輸出移位暫存器	35
圖3.8四位元並列輸入、並列輸出移位暫存器	35
圖3.9八十位元串列輸入、並列輸出移位暫存器	36
圖3.10雙向移位暫存器的操作原理	36
圖3.11反相器	37
圖3.12反相器的特性曲線	38
圖3.13無輸出電容之數位式低壓降線性穩壓器	39
圖3.14輸出電壓穩定圖_重載	40
圖3.15輸出電壓穩定圖_輕載	42
圖3.16輸出電壓穩定圖_重載	43
圖3.17輸出電壓穩定圖_輕載	45
圖3.18線性調節率模擬圖_重載	46
圖3.19線性調節率模擬圖_輕載	48
圖3.20線性調節率模擬圖_重載	49
圖3.21線性調節率模擬圖_輕載	51
圖3.22負載調節率模擬圖_輸入電壓為0.7V	52
圖3.23負載調節率模擬圖_輸入電壓為0.9V	54
圖3.24電路佈局圖	56
圖3.25電路佈局示意圖	57
圖3.26 post-layout simulation輸出電壓穩定圖_重載	58
圖3.27 post-layout simulation輸出電壓穩定圖_輕載	59
圖3.28 post-layout simulation線性調節率模擬圖_重載	61
圖3.29 post-layout simulation線性調節率模擬圖_輕載	62
圖3.30 post-layout simulation負載調節率模擬圖	64
圖3.31量測儀器示意圖	66
圖3.32 Bonding wire之模型	66
圖3.33重載量測圖(負載電流為20mA)	67
圖3.34輕載量測圖(負載電流為1mA)	67
圖3.35重載量測圖(負載電流25mA)	68
圖3.36重載量測圖(負載電流70mA)	69
圖3.37輕載量測圖(負載電流1mA)	69
圖3.38重載量測圖(負載電流85mA)	70









表目錄

表1.1線性穩壓器與切換式穩壓器之特性	2
表2.1 NMOS與PMOS 功率電晶體低壓降線性穩壓器的比較	15
表2.2文獻比較表	29
表3.1預計規格表	40
表3.2 pre-layout simulation results	55
表3.3 pre-sim.與post-sim.比較結果	65

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