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系統識別號 U0002-2108200816271300
中文論文名稱 壓阻式感測器的微小化性能探討
英文論文名稱 A Performance Study of Micro Piezoresistive Sensors
校院名稱 淡江大學
系所名稱(中) 機械與機電工程學系碩士班
系所名稱(英) Department of Mechanical and Electro-Mechanical Engineering
學年度 96
學期 2
出版年 97
研究生中文姓名 楊孟橋
研究生英文姓名 Meng-Chiao Yang
學號 695370279
學位類別 碩士
語文別 中文
口試日期 2008-06-18
論文頁數 92頁
口試委員 指導教授-楊龍杰
委員-張培仁
委員-黃榮堂
委員-李其源
委員-施文彬
中文關鍵字 互補式金氧半導體  懸臂樑  壓電阻  壓阻式感測器 
英文關鍵字 CMOS  cantilever  piezoresistor  piezoresistive sensor 
學科別分類 學科別應用科學機械工程
中文摘要 本研究主要針對CMOS壓阻式微感測器進行一連串的實驗及探討。在經過種種測試與分析皆無法獲得理想之結果後,作者開始重新思考感測器從設計、佈局到後製程實驗流程中,是否有設計不良或是實驗上的缺陷存在,最後本研究將焦點放在壓電阻的線寬上並針對此問題重新設計新型CMOS微型力感測器來探討壓電阻線寬對輸出訊號的影響。
新型感測器由懸臂樑陣列所組成,以二氧化矽做為懸臂樑的材質,多晶矽做為壓電阻的材質。懸臂樑長度從190微米到280微米,寬度從15微米到20微米。壓電阻為惠斯通電橋之全橋佈局,長度從54微米到120微米,寬度從0.9微米到2.0微米。並利用有限元素分析軟體ANSYS模擬各項結構性質並與理論值做比較。
之後探討後製程之實驗流程,包括溼蝕刻以及乾蝕刻,看設計上是否有缺失及需要改進的地方,並利用IntelliSuite軟體進行濕蝕刻的模擬,估算總溼蝕刻的時間。最後利用ANSYS軟體進行靈敏度的預估,約為215 μV/μN。
英文摘要 This research is mainly aimed at the CMOS micro piezoresistive sensor. The author designed a series of experiments to measure the sensors and after all the testing and analysis still could not obtain satisfactory results. So the author try to find if there is any bad design or flaw exists on the experiment from the design, layout to the post-process. Finally the author focus on the width of the piezoresistors and re-design the new CMOS micro force sensors based on the issue and hope to explore the influence of the width of the piezoresistors on output signal.
The new sensors are composed of three cantilever structures, using silicon dioxide as the material of cantilevers, and polysilicon as the material of piezoresistors. The lengths of cantilevers are from 190 μm to 280 μm, the widths are from 15 μm to 20 μm. Moreover, the piezoresistors are arranged as the Wheatstone Bridge circuit, and the lengths of piezoresistors are from 54 μm to 120 μm, the widths are from 0.9 μm to 2.0 μm. Then the theoretical values which calculated by mathematical model of structure is compared to the simulated value with finite element method analyze software, ANSYS.
After the structure simulation, the experiment flow of post-process is subsequently examined, including wet etching and dry etching. The purpose is trying to find out whether there are deficiencies needed to improve. And in this work we also estimate the total wet etching time by IntelliSuite, the simulation result reveals that it takes about 2 hours to release the sensing cantilevers. At last we estimate the output sensitivity according to the simulation results and get the sensitivity about 215μV/μN.
論文目次 目錄
中文摘要......................................................................................I
英文摘要.....................................................................................II
目錄.........................................................................................................IV
圖目錄....................................................................................................VII
表目錄....................................................................................................XII
第一章 緒論..............................................................................................1
1-1 前言.........................................................................1
1-2 研究動機與目的..........................................................3
1-3 文獻回顧...........................................................................6
1-4 論文架構............................................................................11
第二章 CMOS力感測器之實驗與量測................................................12
2-1 CMOS力感測器簡介.......................................................12
2-2 後製程實驗流程與探討.....................................................14
2-2-1溼蝕刻........................................................................14
2-2-2乾蝕刻........................................................................18
2-3 CMOS力感測晶片之封裝及量測.....................................20
2-3-1 OP之量測.................................................................20
2-3-2 壓電阻量測...............................................................24
2-4 結果與討論.........................................................................32
第三章 新型CMOS力感測器之設計...................................................35
3-1 設計原理.............................................................................35
3-1-1 壓電阻設計...............................................................35
3-1-2 懸臂樑尺寸設計.......................................................46
3-2 懸臂樑有限元素分析.........................................................50
3-3 感測器佈局設計.................................................................55
第四章 後製程與輸出靈敏度之模擬與分析........................................60
4-1 濕蝕刻.................................................................................60
4-2 乾蝕刻.................................................................................68
4-3 CMOS力感測器之靈敏度預估.........................................69
4-3-1 正常尺寸懸臂樑之靈敏度預估...............................69
4-3-2 增加施力平板之懸臂樑靈敏度預估.......................73
4-4加入運算放大器改善後製程及量測上的缺點..........77
4-5 CMOS力感測晶片之量測方法.........................................80
第五章 結論與未來方向........................................................................82
5-1 結論.....................................................................................82
5-2 未來方向.............................................................................84
參考文獻..................................................................................................87
附錄A 後製程失敗經驗.........................................................................90

圖目錄
圖1-1 委託CIC代工之壓力計陣列晶片................................................4
圖1-2 委託CIC代工之力感測器............................................................4
圖1-3 CMOS 0.8 μm DPDM製程之壓力感測器其壓電阻線寬........7
圖1-4 懸臂樑陣列....................................................................................8
圖1-5 壓電阻線寬....................................................................................8
圖1-6 二維壓阻式力感測器之壓電阻寬度............................................9
圖1-7 單顆CMOS力感測晶片之尺寸...................................................9
圖1-8 CMOS力感測器之壓電阻尺寸設計.........................................10
圖1-9 論文架構......................................................................................11
圖2-1 力感測晶片整體實際佈局圖......................................................13
圖2-2 六種感測薄膜構形之佈局設計..................................................13
圖2-3 製程堆疊示意圖..........................................................................15
圖2-4 未蝕刻前晶片上視圖..................................................................15
圖2-5 硫酸加雙氧水蝕刻液蝕刻60分鐘後之情形............................16
圖2-6 反應離子蝕刻機(RIE).............................................................18
圖2-7 CF4蝕刻20分鐘後,晶粒之外觀.............................................18
圖2-8 以SEM觀察CF4蝕刻20分鐘後,感測器之外觀..................19
圖2-9 運算放大器..................................................................................21
圖2-10 OP電路圖..................................................................................21
圖2-11 OP打線圖..................................................................................22
圖2-12 100 μV電壓輸入......................................................................23
圖2-13 數位式電表................................................................................23
圖2-14 電路版光罩................................................................................24
圖2-15 玻璃電路版................................................................................24
圖2-16 nanoindenter全貌......................................................................25
圖2-17 nanoindenter內部之施力壓頭..................................................25
圖2-18 以探針量測電阻值....................................................................26
圖2-19 單一壓電阻之阻值....................................................................27
圖2-20 薄膜厚度1.21 μm,20 μN施力下之變形量...........................29
圖2-21 薄膜厚度4.475 μm,20 μN施力下之變形量..........................29
圖2-22 施力(藍色)對位移(紅色)關係圖....................................31
圖2-23 (a) ~ (d) 施力狀態下之電阻值變化連拍...............................31
圖2-24 壓電阻與懸臂樑邊緣之距離d.................................................32
圖2-25 溼蝕刻後之壓電阻....................................................................32
圖2-26 TSMC 0.35 μm 2P4M製程剖面圖........................................33
圖3-1 惠斯通電橋..................................................................................36
圖3-2 壓電阻佈置圖..............................................................................36
圖3-3 只有一個電阻變化之全橋結構..................................................37
圖3-4 兩個同側壓電阻變化之全橋結構..............................................38
圖3-5 兩個對稱壓電阻變化之全橋結構..............................................39
圖3-6 兩個壓電阻一正一負變化之半橋結構......................................40
圖3-7 只有R1變化之半橋結構............................................................40
圖3-8 只有R2變化之半橋結構............................................................41
圖3-9 一正一負電阻值變化之設計.....................................................43
圖3-10 壓電阻佈值於上表面及下表面之設計...................................43
圖3-11 最終壓電阻配置圖...................................................................44
圖3-12 五種壓電阻尺寸.......................................................................45
圖3-13 各懸臂樑佈局圖.......................................................................49
圖3-14 懸臂樑剖面圖...........................................................................50
圖3-15 懸臂樑網格分割圖形...............................................................51
圖3-16 懸臂樑z方向變形圖..............................................................51
圖3-17 懸臂樑y方向應力分布圖......................................................52
圖3-18 懸臂樑y方向應變分布圖......................................................52
圖3-19 壓電阻與中性軸之關係圖.......................................................53
圖3-20 結構堆疊示意圖.......................................................................55
圖3-21 (a)contact (b)metal-1 (c)via12 (d)metal-2.............................56
圖3-22 (a)via23 (b)metal-3 (c)via34 (d)metal-4 (e)保護層...............57
圖3-23 壓電阻與懸臂樑邊緣之間距....................................................58
圖3-24 整體晶片佈局圖........................................................................59
圖4-1 濕蝕刻流程示意圖......................................................................62
圖4-2 IntelliSuite之濕蝕模擬刻操作介面........................................63
圖4-3 70℃、30 wt%之KOH溶液蝕刻30分鐘的情形................65
圖4-4 80℃、10 wt%之TMAH溶液蝕刻2小時的情形...............65
圖4-5 側向觀察懸臂樑根部未蝕刻完成之情形..................................66
圖4-6 80℃、10 wt%之TMAH溶液蝕刻2.5小時的情形..............66
圖4-7 80℃、10 wt%之TMAH溶液蝕刻3小時的情形.................67
圖4-8 側向觀察蝕刻完成之情形..........................................................67
圖4-9 乾蝕刻流程圖..............................................................................68
圖4-10 懸臂樑網格分割圖形-二維.......................................................70
圖4-11 懸臂樑z方向變形圖-二維.......................................................70
圖4-12 懸臂樑y方向應力分布圖-二維...............................................71
圖4-13 懸臂樑y方向應變分布圖-二維...............................................71
圖4-14 各組懸臂樑之預估靈敏度........................................................72
圖4-15 施力平板與懸臂樑之尺寸關係................................................73
圖4-16 增加施力平板後懸臂樑z方向變形圖....................................74
圖4-17 增加施力平板後懸臂樑y方向應力分布圖.............................74
圖4-18 增加施力平板後懸臂樑y方向應變分布圖.............................75
圖4-19 有施力平板的懸臂樑佈局圖....................................................75
圖4-20 各組新型懸臂樑之預估靈敏度................................................76
圖4-21 運算放大器示意圖....................................................................77
圖4-22 運算放大器佈局圖....................................................................78
圖4-23 懸臂樑加運算放大器之佈局圖................................................79
圖4-24 靜態量測架構示意圖................................................................80
圖4-25 動態量測架構示意圖................................................................81
圖5-1 利用PDMS封裝CMOS力感測晶片........................................84
圖5-2 懸臂樑向右旋轉三度..................................................................85
圖5-3 旋轉角度後之蝕刻情形..............................................................86
圖A-1 硫酸加雙氧水混合液浸泡時間不足之蝕刻情形.....................90
圖A-2 以KOH蝕刻120分鐘後,晶粒受損情形..............................91
圖A-3 以KOH蝕刻30分鐘後,晶粒外觀........................................91
圖A-4 因擴孔而導致結構損壞.............................................................92






表目錄
表2-1 1.21 μm膜厚之感測器在不同施力下之電阻變化及靈敏度....30
表2-2 4.475 μm膜厚之感測器在不同施力下之電阻變化及靈敏度..30
表3-1 在室溫中的壓阻係數值..............................................................47
表3-2 各組懸臂樑之尺寸......................................................................49
表3-3 二氧化矽與氮化矽之機械材料性質..........................................50
表3-4 1 μN施力下理論與模擬數值比較...........................................54
表4-1 濕蝕刻所選用之蝕刻液..............................................................60
表4-2 乾蝕刻後之懸臂樑尺寸..............................................................69
表4-3 厚度6.155 μm、1 μN施力下理論與模擬數值比較...................72
表4-4 加入施力平板後各懸臂樑的尺寸..............................................73
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