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系統識別號 U0002-2106200715180600
中文論文名稱 應用虛擬測試存取機制以提升系統單晶片測試效率之排程演算法
英文論文名稱 An Efficient Virtual-TAM Based Algorithm for SOC Test Scheduling
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 95
學期 2
出版年 96
研究生中文姓名 吳健序
研究生英文姓名 Chien-Hsu Wu
學號 694390021
學位類別 碩士
語文別 英文
口試日期 2007-06-13
論文頁數 49頁
口試委員 指導教授-饒建奇
委員-陳竹一
委員-李建模
中文關鍵字 超大型積體電路測試  單晶片系統測試  排程 
英文關鍵字 SOC Testing  TAM  Test Scheduling 
學科別分類 學科別應用科學電機及電子
中文摘要 隨著半導體產業快速發展,系統晶片(System on Chip)的想法逐漸發展成型,一顆系統晶片包含了微處理器(CPU)、數位訊號處理器(DSP)、記憶體等基本部分,隨著應用在不同領域也會加入不同的模組如無線辨識系統(RFID)、衛星定位系統(GPS)、影像解碼器(Video Decoder)等,如此一來在一塊晶片上面將包含了許多的矽智財(IP, Intellectual Properties),不過,當晶片是經由各種矽智財所組合而成時,晶片的測試就變的格外的重要和困難。
爲了完整的測試矽智財,我們必須加上測試接收機制(TAM, Test Access Machine)、測試包裝機制(Test Wrapper)、內部掃描串(Internal Scan Chains)等機制。測試向量與控制訊號將藉由測試接收機制從系統晶片的接腳到矽智財輸入(輸出)接腳與內部掃描串,內部掃描串的功用主要是用來使矽智財內部暫存器可以被外部的系統晶片讀取,測試包裝機制的使用可以確保所有的矽智財是獨立被測試。爲了達到百分之百的錯誤涵蓋率,需要使用非常大量的測試向量,將這些測試向量位移到掃描串將需要大量的時間,因此需要一個好的測試排程來降低這些轉移的時間。
此篇論文主要是在設計測試排程的部份,在這篇論文裡面我們提出了一個架構與有效的方法來決定系統晶片的排程,我們參考虛擬測試接收機制(Virtual TAM)提出了虛擬控制訊號(Virtual Control Signal)的架構,我們使用這個架構來有效的增加測試寬度(TAM Widths),我們的方法結合了傳統的掃描串列與多重輸入串架構(RMSC, Reconfigurable Multiple Scan Chains)且配合上改良的TR-Architecture演算法。TR-Architecture演算法分為四個步驟來處理測試排程分別為:(1) Creating a Start Solution (2) OPTIMIZE-BOTTOMUP (3) OPTIMIZE-TOPDOWN (4) Reshuffle。我們基於這些步驟再加上兩個演算法配合,以達到降低測試時間的目的。我們將我們提出的方法用在ITC’02 SOC TEST Benchmarks,獲得了較好的測試時間。
英文摘要 In modern system-on-a-chip (SOC) design, a chip always contains multiple cores. The method of testing the chip becomes an important issue. In order to test the chip completely, a test access machine (TAM), test wrapper for each core and internal scan chains within each core is required. Test data and test control signal will be sent to I/O and internal scan chains from SOC pins by TAM. Internal scan chain allows the registers to be transparent. The test wrapper is used to confirm that each core at SOC chip can be tested independently. For one hundred percent of test coverage, it needs a large number of test patterns. Shifting those test data into scan chains will take a significant amount of time. Therefore a test schedule is required to reduce test application time.
This paper presents a framework and an efficient method to determine SOC test schedules. We increase the test TAM widths by the framework. Our method deals with the traditional scan chains and reconfigurable multiple scan chains. Experimental results for ITC’02 SOC TEST Benchmarks show that we obtain better test application time when compared to previously published algorithms.
論文目次 TABLE OF CONTENTS



中文摘要 ..……………………………………………………………………………… I
英文摘要 ...……………………………………………………………........................... III
Table of Contents …………………………………………….................................... V

List of Figures ………………………………………………...................................... VII

List of Tables …………………………………………………………………………. IX


Chapter 1 INTRODUCTION ………………….…………………..………… 1

1-1 Motivation …………………………………………………………………............ 1
1.1.1The Development of Design Flow ..………………………………….…. 2
1-2 Test Challenges in Core-based SOC Design ...………………..………. 5
1.2.1 Core test access ………....…..……………………………………………….. 6
1-3 TAM Architecture ..……………………………………………………………… 8
1.3.1 Basic TAM Architecture .……………………………………………. 9
1.3.2 Test Bus Architecture ..……………………….……………..………………. 11
1.3.3 TestRail Architecture ...…......……………………………………….............. 12
1-4 Wrapper Architecture ………………………………………………………….. 14

Chapter 2 BASIC CONCEPTS ……………………..………………………. 16

2-1 Design foe Testability ...…………………………………………………………. 16
2.1.1 Circuit Defects and Faults ………………………………………………….. 16
2.1.2 Fault Detection ………………………………………………………............. 17
2-2 The popular rectangle packing model .…………………………………….. 19
2-3 The general test schedule ………….……………..……………………..……... 22
2.3.1 Serial test architecture ……………….……………………………...……… 22
2.3.2 Parallel test schedule …………………..…………………………….……… 23
2.3.3 Mixed test schedule ……………………………………..………..…………. 23

Chapter 3 PREVIOUS METHODOLOGIES ………………………. 24

3-1 Reconfigurable Multiple Scan Chains ..........……………………………….. 24
3.1.1 Variable definitions …………………………………………………………. 25
3.1.2 Test Sessions …………………………………………………………………. 26
3.1.3 Chain Cycles ………………………………………………………………… 27
3.1.4 Control Signals ……………………………………………………………… 28
3-2 TR Architecture ..………………………………………………………………… 29

Chapter 4 OUR ARCHITECTURE AND ALGORITHM …….............. 36

4-1 Virtual Enable Signal …………………………………………………………... 36
4-2 Our Algorithm ……………………………………………………………………. 38

Chapter 5 SIMULATION RESULTS ………………………………….. 42

Chapter 6 CONCLUSIONS ………………………………………………… 46

References ……………………………………………………………………………. 47

LIST OF FIGURES



Figure 1.1 an example of SOC ...…...……………………………...……………. 2
Figure 1.2 a simplified chip design flow and industry relationships …………. 3
Figure 1.3 system design flow using core cells …………………………………. 4
Figure 1.4 Overview of the test access in an embedded-core test …..………… 7
Figure 1.5 the test access architecture overview ……………………………….. 9
Figure 1.6 (a) multiplexing Architecture (b) daisychain Architecture (c)
distribution Architecture …………………………………………… 11
Figure 1.7 (a) a Test Bus Architecture (b) a possible corresponding
serial test schedule ……………………………………………........... 12
Figure 1.8 (a) a TestRail Architecture (b) a possible corresponding
serial (c) a parallel test schedules ……………………………........... 13
Figure 1.9 core test wrapper ……………………………………………………. 15
Figure 2.1 an overview of scan chain …………………………………………… 16
Figure 2.2 an example of core test time ………………………………………… 18
Figure 2.3 a TAM design using TAM width partition ………………………… 19
Figure 2.4 test schedule of Figure 2.3 ……………………………………........... 20
Figure 2.5 an example rectangle for Core 6 in SOC p93791 ………………….. 20
Figure 2.6 TAM design using generalized rectangle packing ………………… 21
Figure 2.7 test schedule of Figure 2.6 ……………………………………........... 21
Figure 2.8 an example of the serial test schedules ………………………........... 22
Figure 2.9 an example of the parallel test schedules ……………………........... 23
Figure 2.10 an example of the mixed test schedules …………………………….. 23
Figure 3.1 the example of Reconfigurable Multiple Scan ……………….......... 25
Figure 3.2 an example of test sessions …………………………………….......... 26
Figure 3.3 Scan Chains for test session 1 of the example SOC ………….......... 27
Figure 3.4 The registers bypassed by Ctrl1 ……………………………………. 27
Figure 3.5 Scan Chain for test session 2 of the example SOC ………………… 28
Figure 3.6 Algorithm of Creating a Start Solution ............................................. 30
Figure 3.7 Algorithm of OPTIMIZE-BOTTOMUP ........................................... 31
Figure 3.8 Algorithm of OPTIMIZE-TOPDOWN ............................................. 34
Figure 3.9 Algorithm of Reshuffle ........................................................................ 35
Figure 4.1 Virtual TAM architecture ……………………………………........... 37
Figure 4.2 virtual control signal ………………………………………………… 38
Figure 4.3 Algorithm of Compute_Time ……………………………………….. 39
Figure 4.4 Algorithm of registers assignment ………………………………….. 40
參考文獻 [1] International SEMATECH. The International Technology Roadmap for Semiconductors (ITRS): 2001 Edition. http://public.itrs.net/Files/2001ITRS/Home.htm, 2001.
[2] R.K. Gupta, Y. Zorian, “Introducing Core-Based System Design,” In Proceedings IEEE Design & Test of Computers, Volume: 14, Issue: 4, pp. 15 - 25, Oct.-Dec. 1997.
[3] M. Keating and P. Bricaud, “Reuse Methodology Manual For System-on-Chip Designs.” Kluwer Academic Publishers, 1998.
[4] Yervant Zorian, Erik J. Marinissen, and Sujit Dey, “Testing Embedded-Core Based System Chips”, In proceedings IEEE International Test Conference, pp 130-134, 1998.
[5] J. Aerts and E.J. Marinissen, “Scan Chain Design for Test Time Reduction in Core-Based ICs,” In Proceedings IEEE International Test Conference (ITC), pp. 448-457, Washington, DC, Oct. 1998.
[6] Venkata Immaneni and Srinivas Raman. “Direct Access Test Scheme-Design of Block and Core Cells for Embedded ASICS,” In Proceedings IEEE International Test Conference (ITC), pp. 488-492, Sep. 1990.
[7] IEEE P1500 Web Site, http://grouper.ieee.org/groups/1500/.
[8] Yervant Zorian. “A Distributed BIST Control Scheme for Complex VLSI Devices,” In Proceedings IEEE VLSI Test Symposium, pp. 6-11, April 1993.
[9] V. Iyengar, K. Chakrabarty et al. “On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization,” In Proceedings IEEE VLSI Test Symposium (VTS), 2002, pp. 253-258.
[10] V. Iyengar, K. Chakrabarty and E.J. Marinissen, “Test wrapper and test access mechanism co-optimization for system-on-chip,” Proceeding of J. Electronic Testing: Theory and Applications, vol. 18, pp.211-228, March 2002.
[11] E.J. Marinissen et al, “A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores,” In Proceedings IEEE International Test Conference (ITC), pp. 284-293, Washington, DC, Oct. 1998.
[12] S.K. Goel and E.J. Marinissen, “A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips,” Journal of Electronic Testing: Theory and Applications, 2003, pp. 425-435.
[13] Vikram Iyegnar, Krishnendu Chakrabarty, and Erik Jan Marinissen, “Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip”, In Proceedings IEEE International Test Conference, pp 1023-1032, 2001.
[14] Chakrabarty, K., “Optimal test access architectures for system-on-a-chip”, ACM Trans Design Automation of Electronic Systems, 2001, pp. 26-49.
[15] Goel, S.K.; Marinissen, E.J., “Effective and efficient test architecture design for SOCs”, Test Conference, Proceedings. International, 2002, pp. 529-538.
[16] R.L. Graham. Bounds on Multiprocessing Anomalies. SIAM Journal of Applied Mathematics, 17”416-429,1969.
[17] Joep Aerts and Erik Jan Marinissen. “Scan Chain for Test Time Reduction in Core-Based ICs.” In Proceedings IEEE International Test Conference (ITC), pages 448-457, Washington, DC, October 1998.
[18] Qiang Xu; Nicolici, N., “Multifrequency TAM design for hierarchical SOCs”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, Vol.25, No.1, 2006, pp. 181-196.
[19] Chakrabarty, K., “Optimal test access architectures for system-on-a-chip”, ACM Trans Design Automation of Electronic Systems, 2001, pp. 26-49.
[20] Quasem, Md.S.; Gupta, S., “Designing reconfigurable multiple scan chains for systems-on-chip”, VLSI Test Symposium, Proceedings. 22nd IEEE, 2004, pp. 365-371.
[21] Erik J. Marinissen, Vikram Iyegnar, and Krishnendu Chakrabarty, “ITC2002 SOC benchmarking initiative”, http://www.extra.research.philips.com/itc02socbenchm.
[22] Iyengar, V.; Chakrabarty, K.; Marinissen, E.J., “Efficient Wrapper/TAM Co-Optimization for Large SOCs”, Design, Automation and Test in Europe Conference and Exhibition, Proceedings, 2002, pp. 491-498.
[23] Iyengar, V.; Chakrabarty, K.; Marinissen, E.J., “On using rectangle packing for SOC wrapper/TAM co-optimization”, VLSI Test Symposium, (VTS 2002). Proceedings 20th IEEE, 2002, pp. 253-258.
[24] Goel, S.K.; Marinissen, E.J., “Cluster-based Test Architecture Design for System-on-Chip”, VLSI Test Symposium, (VTS 2002). Proceedings 20th IEEE, 2002, pp. 259-264.
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