由於現在的科技越來越進步，人們的渴望的需求也慢慢的提升，積體電路設計來滿足未來生活機能，以40奈米慢慢的提高到16奈米，由於現在三維積體電路堆疊技術開啟了科技的新方向，使得在一些生活機能裝置的發展對積體電路設計要求也會越來越多也會越做越小來滿足生活機能。現在的三維積體電路比之前的二維積體電路設計不僅可以加入更多的電晶體，提升連線密度、減小外觀尺寸、提升效率、降低生產費用、不限制裸晶、減少繞線長度、堆疊來達到製程技術，而且現在的三維積體電路堆疊技術連接的分別為矽穿孔(Through silicon via ,TSV)是比較常用的方式，由於為了讓矽穿孔(Through silicon via ,TSV)數量減少來達到成本上的考量，以及現在三維積體電路在設計上仍難要如何解決散熱上的問題以及避免漏電流的問題。

more and more technological advances, people's desire demand has slowly improved, integrated circuit design to meet future life functions, slowly at 40 nm to 16 nm, due to the now three-dimensional stacked integrated circuits technology opens up new directions in technology, making some life functions in the development of the integrated circuit device design requirements will be more and more will get smaller to meet life function. Dimensional integrated circuit design now than before the three-dimensional integrated circuits can not only add more transistors to enhance the connection density, reducing the appearance of size, improve efficiency, reduce production costs, does not limit the die, reducing the winding length stacked to achieve process technology, and now the three-dimensional integrated circuit stacking technology connections are silicon perforation (Through silicon via, TSV) is a more common way, because in order to make silicon perforation (Through silicon via, TSV) to reduce the number to achieve cost considerations, and now three-dimensional integrated circuits is still hard to be on how to solve the problem in the design of the heat and to avoid leakage problems.

誌謝......I
中文摘要..II
Abstract..III
目錄......IV
圖片列表..VI
表格列表..VII
Chapter1. 緒論.......................1
1-1研究背景與動機....................1
1-2研究動機與目的....................3
1-3 論文架構.........................5
Chapter 2.相關文獻與回顧.............7
2-1何謂三維積體電路設計..............7
2-2 2D FPGA和3D FPGA架構設計.........9
2-3 三維平面規劃....................11
2-4 模擬退火法......................12
2-5 KL演算法........................13
2-6矽晶穿孔(Through-Silicon Via)....14
Chapter 3. 研究方法.................15
3-1概述.............................15
3-2平面規劃.........................16
3-3階層表示.........................18
3-4層級切割.........................20
3-4群聚.............................23
3-5 TSV篩選與配置...................24
3-6 配對法..........................25
Chapter 4 研究結果..................26
4-1實驗環境.........................26
4-2實驗結果.........................26
Chapter 5 結論與未來展望............31
5-1結論.............................31
5-2未來展望.........................32
參考文獻............................33

圖片列表
圖1-1 積體電路設計演化圖..................................2
圖1-2 TSV(Through-Silicon via)與模組連線圖................4
圖2-1 FPGA內部結構圖......................................8
圖2.2 Face to Face、Face to Back、Back to Back...........10
圖2.3 模擬退火表示圖.....................................12
圖2.4 模組連線關係圖.....................................13
圖2.5 TSV連線關係圖........................... ..........14
圖3.1 系統流程圖.........................................15
圖3.2 序列表示...........................................16
圖3.3 矽穿孔最佳位置圖...................................17
圖3.4 階層式表示法.......................................19
圖3.5 面積不平衡.........................................20
圖3.6 透過D-value改善面積不平均..........................21
圖3.7 面積平衡表示圖.....................................22
圖3.8 模擬組合法.........................................23
圖3.9 由下到上方式依序往上掃描...........................24
圖3.10 配對法表示圖......................................25
圖4.1 面積使用貪婪法表示圖...............................27
圖4.2 以三層n100、n200、n300時間比較.....................29

表格列表
表4.1 Co-place與Our時間比較..............................28
表4.2 與Co-place TSV數量差異.............................29
表4.3 各測試電路產生的TSV數量............................30

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