淡江大學覺生紀念圖書館 (TKU Library)
進階搜尋


下載電子全文限經由淡江IP使用) 
系統識別號 U0002-2006200518024100
中文論文名稱 高效能互補式金氧半邏輯電路與功率效能關切之算術電路架構在深次微米製程技術上的設計與分析
英文論文名稱 Design and Analysis of High-Performance CMOS Logic Circuits and Power-Aware Arithmetic Circuit Structures on the Deep-Submicron Process Technology
校院名稱 淡江大學
系所名稱(中) 電機工程學系博士班
系所名稱(英) Department of Electrical Engineering
學年度 93
學期 2
出版年 94
研究生中文姓名 鄭舜文
研究生英文姓名 Shun-Wen Cheng
學號 686390096
學位類別 博士
語文別 英文
口試日期 2005-04-29
論文頁數 129頁
口試委員 指導教授-鄭國興
委員-蔡加春
委員-江正雄
委員-李揚漢
委員-蔡宗漢
中文關鍵字 功率效能關切  混合邏輯  帶通電晶體邏輯  條件和加法器  條件進位  雙臨限電壓  多重臨限電壓互補金氧半  互補金氧半 
英文關鍵字 power-aware  hybrid logic  pass-transistor logic  conditional sum adder  conditional carry  dual-threshold voltage  MTCMOS  CMOS 
學科別分類
中文摘要 功率消耗總是可攜式行動系統的首要考量,而在高效能系統、工作站系統亦如是。製程技術持續進步的一個結果,就是使得「降低每個邏輯電路的功率消耗、但增進其操作速度」,成為時下互補式金氧半(CMOS)晶片設計的普遍共識。這共識將帶領我們進入深次微米時代。
本論文先從各個方向來看深次微米電子學上不同的高速、低功率電路設計。首先吾人提出一個可以實現任意邏輯函數的混合邏輯程序─俱優先權之首要原項拼圖(PPIPP)─依循這個程序,可以得到一個新的混合邏輯電路族系。此程序以最少數目的電晶體來實現邏輯函數,而且所實現之電路在所有節點上都有全擺幅的電壓差,有著對於深次微米電晶體尺寸縮小和操作電壓縮減的高強健性。在雙端差動之數位應用領域上,介紹了低功率電流偵測互補式帶通電晶體邏輯設計(LCSCPTL)。在低的操作電壓之下,電流偵測機構比起電壓偵測機構擁有較快的感應速度,所以此邏輯電路的操作速度快於傳統的互補式帶通電晶體邏輯(CPL)電路。論文的第一部分,以兩個真單相時脈(TSPC)邏輯電路的改進電路的討論做一個結束。這兩個改進電路分別是非全電壓擺幅真單相時脈(NSTSPC)電路與全NMOS真單相時脈(ANTSPC)電路。ANTSPC邏輯電路使用NMOS取代PMOS,因而有效減少了Φ-區段的輸出負載,並得到較高的ΦB-區段佈局密度。藉著交替使用NSTSPC與ANTSPC,成功的建構了一個無須PMOS、真單相時脈的高速管線結構。
論文的第二部分,談到功率效能關切之算術電路架構。傳統的「低功率設計」與所謂「功率效能關切設計」的不同,在於「低功率設計」的目標在於如何把功率消耗降到最低;而「功率效能關切設計」是在有限的功率消耗配額上,如何提升其他效能指標到最大。功率效率正開始變成數位訊號處理(DSP)的重要指標;而該數位訊號處理的效能是由所配置的加法器來主導。在高速算術應用領域中,條件和加法器(CSA)已展現其優異性能。本研究對條件和加法器做出改進,提出一個更優異的加法器,稱之為條件進位加法器(CCA)。此條件進位架構不只適用於加法器,亦適用於減法器、數值比較器與排序器的實現。條件進位加法器的改進,減少了多工選擇器與內部節點的數目,有效降低功率消耗,與增進操作速度。在所提架構之下,吾人以單端CMOS、雙端差動之CPL與LCSCPTL不同邏輯電路實現32位元條件和加法器與條件進位加法器,並做了詳細的分析比較。
到目前為止,降低開關時的動態功率消耗,是許多低功率電路技術的首要目標。因而認為關閉狀態下的漏電流所造成的功率消耗,相較於動態功率消耗,是可忽略不計的。然而,當製程技術向深次微米大歩跨進,漏電流所消耗的功率大增,不可再等閒視之。對此,多重臨限電壓互補金氧半(MTCMOS)技術的出現,日益受到歡迎。此技術抑制了隨製程進歩而逐步上升的漏電流功率消耗,並維持了高效能的目標。為了找出最具功率效能的架構,以台積電0.25微米單層矽化物、五層金屬(1P5M+)多重臨限電壓CMOS製程技術為平台,吾人提出六個64位元、混合雙臨限電壓條件進位加法器架構加以討論。在緊要關鍵路徑上的元件採用低臨限電壓電晶體以加快操作速度;而在其他路徑上的元件採用高臨限電壓電晶體以節省功率。如此,非常有益於實現功率效能關切的架構。經比較後發現,其中之一的電路架構有著最低的功率-延遲乘積與最低的能量-延遲乘積。此雙臨限電壓架構展現出功率與效能的良好妥協,其功率效率優於其他任何單一臨限電壓架構設計。
英文摘要 Power dissipation is always a major design consideration for mobile, portable systems as well as high-performance, workstation systems. Decreasing power consumption but increasing operation speed per logic circuit has become a general awareness in almost all CMOS chips designed nowadays as a result of the lasting progress in processing technology that has led us into the deep-submicron era.
The dissertation first deals with the different aspects of low-power high-speed logic circuits for deep-submicron electronics. A hybrid logic synthesis procedure for arbitrary logic function was proposed. Following the proposed procedure, Prioritized Prime Implicant Patterns Puzzle (PPIPP), may get a new hybrid logic circuit family. The PPIPP gets a mixed logic with minimum transistor count, and it has full-swing signal in all nodes and high robustness against transistor downsizing and voltage scaling. For differential-end digital applications, a Low-power Current-Sensing Complementary Pass-Transistor Logic (LCSCPTL) was introduced. The current-sensing scheme yields a faster sensing speed under small voltage swing than the voltage-sensing scheme; hence the operation speed of LCSCPTL is faster than conventional CPL. The first part ends up with the discussions of two improved dynamic circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Non-full Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The ANTSPC uses NMOS transistors to replace PMOS transistors; the output loading of Φ-Section is therefore reduced and a higher layout density of ΦB-Section is obtained. By using the techniques of NSTSPC and ANTSPC alternately, a high-speed, TSPC pipelined structure without PMOS logic block was successfully constructed.
The second part gives the proposed architecture and circuit techniques for the power-aware arithmetic applications. The difference between conventional low-power design and power aware design is that whereas low-power design refers to minimizing power, yet power-aware design refers to maximizing some other performance metric, subject to a power quota. The power efficiency is becoming an important index of digital signal processing (DSP), and the performance of DSP is predominantly determined by its adder. The Conditional Sum Adder (CSA) has been shown to outperform other adders applied in high-speed arithmetic applications. This investigation proposes a modified CSA called the conditional carry adder (CCA). Besides, the conditional carry architecture can be used on subtractor, integer comparator and sorter design. Architectural modification of the CCA lowers the number of multiplexers and internal nodes, effectively decreases the power dissipation and raises the operation speed. Based on the proposed scheme, 32-bit CSAs and CCAs by CMOS, CPL and LCSCPL were carefully compared and analyzed.
Up to now, reducing the switching dynamic power dissipation was the primary focus in many of the proposed low-power circuit techniques. Hence the off-state leakage power was neglected compared to dynamic power. However, as technology scales into the deep-submicron age, the increase in leakage power can no longer be ignored. Therefore the Multi-Threshold voltage CMOS (MTCMOS) technology has appeared as an increasingly popular technique to restrain the escalating leakage power, while keeping the goal of high performance. Based upon TSMC 0.25µm Single-layer Salicide 5-layer Metal (1P5M+) MTCMOS Process technology, six 64-bit hybrid dual-threshold CCAs for power-aware applications were presented systematically. Components on critical paths use a low threshold voltage to accelerate the speed of operation, and other components use the normal threshold voltage to save power. This feature is very useful in implementing power-aware arithmetic systems. One of the proposed circuits has the lowest power-delay product and energy-delay product. The hybrid circuit represents a fine compromise between power and performance; its power efficiency is better than that of the single threshold voltage circuit designs.
論文目次 Chapter 1 Introduction ..................................1
1.1 Evolution of the VLSI ...............................1
1.2 Power Dissipation in CMOS Digital Circuits ..........2
1.2.1 Dynamic Power Dissipation .........................3
1.2.2 Short-Circuit Power Dissipation ...................5
1.2.3 Static Power Dissipation ..........................6
1.2.3.1 DC Power Dissipation ............................6
1.2.3.2 Leakage Power Dissipation .......................7
1.3 Various CMOS Logic Circuits..........................10
1.3.1 Single-end logic: CMOS vs. pass-transistor logic...10
1.3.2 Differential-end logic: complementary pass-transistor logic...11
1.3.3 Dynamic logics ....................................12
1.4 Conventional Adder Schemes ..........................15
1.4.1 Ripple Carry Adder ................................15
1.4.2 Carry Lookahead Adder and Manchester Carry-Chain...16
1.4.3 Carry Select Adder ................................18
1.4.4 Parallel Prefix Adders ............................19
1.4.4.1 Brent-Kung Adder ................................20
1.4.4.2 Ladner-Fischer Adder ............................22
1.4.4.3 Kogge-Stone Adder ...............................22
1.4.4.4 Han-Carlson Adder ...............................22
1.4.5 Conditional Sum Adder ............................24
1.5 Thesis Organization ................................25

Chapter 2 Prioritized Prime Implicant Patterns Puzzle for Logic Synthesis...28
2.1 Motivation of Logic Minimization....................28
2.2 Basic Circling Concepts ............................29
2.2.1 Square of the Karnaugh map (K-map) ...............29
2.2.2 Modified K-map ...................................30
2.2.3 Loop Circling for Simplification .................30
2.2.4 Selected Set of Control Variables ................31
2.2.5 Implicate Loop ...................................32
2.2.6 Circuit Implementation Methods ...................32
2.3 Prioritized Prime Implicant Patterns Puzzle (PPIPP)...32
2.4 Comparisons of Various Logics.........................35
2.5 Summary of the Hybrid Logic by PPIPP..................39

Chapter 3 Low-Power Current-Sensing Complementary Pass-Transistor Logic...40
3.1 Basic Concept of Differential-end Digital Logic ....40
3.2 Circuit Structure and Operational Principle ........43
3.2.1 The CSCPTL Circuit ...............................44
3.2.2 The LCSCPTL Circuit ..............................48
3.3 Performance Comparisons of CPL, CSCPL and LCSCPL ...51
3.4 Chapter Summary ....................................54

Chapter 4 ALL-N-Transistor TSPC Logics ..................56
4.1 Introduction to True-Single Phase Clocking Logic (TSPC) ...56
4.2 Circuit Structures and Operational Principles ......58
4.2.1 Non-full Voltage Swing TSPC (NSTSPC) .............58
4.2.2 All-N-Block TSPC (ANTSPC) ........................60
4.3 Performance Evaluations and Comparisons ............63
4.3.1 Stacks of the MOS Transistors ....................63
4.3.2 Maximum Operation Frequency ......................64
4.4 64-Bit Hierarchical Pipeline Adder Circuit Implementation...67
4.5 Summary of the All-N TSPC Logics....................70

Chapter 5 Mechanisms of Conditional Carry ...............71
5.1 Conditional Sum Adder (CSA) ........................71
5.2 Conditional Carry Architecture .....................75
5.2.1 Conditional Carry Addition Rules .................75
5.2.2 Construction of Conditional Carry Adder (CCA) ....76
5.3 Comparisons of CSA and CCA .........................80

Chapter 6 Implementation and Analysis of Conditional Carry Adder (CCA)...84
6.1 Circuit Implementations of 32-Bit Conditional Carry Adder by CMOS, CPL and LCSCPTL...84
6.2 64-bit Dual-threshold Voltage Conditional Carry Adder Designs...92
6.2.1 Multi-Vth Design Concept .........................92
6.2.2 Construction of Hybrid Architectures .............94
6.2.3 Simulation Results and Comparisons ...............103
6.2.4 Summary of the Power-Aware Design ................105
6.3 High-Speed 64-bit Integer Comparator using Conditional Carry Mechanism...107
6.3.1 Introduction to Integer Comparator and Hardware Sorter...107
6.3.2 Modified 1's Complement for Comparator Design ....109
6.3.3 Proposed Comparator Architecture .................111
6.3.4 Summary of the Comparator Design .................113

Chapter 7 Concluding Remarks ............................115

Bibliography ............................................118
Appendix A Related Publication List .....................127


List of Tables
Table 2.1 Various circuit comparison results of the full swing 2-input XOR function .....37
Table 4.1 Power dissipation and maximum frequency of the 64-bit adder under various MOS models ...69
Table 5.1 Leading control carry of the CSA and the CCA .............79
Table 5.2 Comparisons of 2-to-1 multiplexer numbers of the CSA and the proposed CCA .....83
Table 6.1 Layout area comparisons of 32-bit CSAs and CCAs ..........89
Table 6.2 Three threshold voltage types of TSMC 0.25µm 1p5m+ CMOS Process Technology .....93
Table 6.3 Comparisons of multiplexer number of 64-bit power-aware CCAs ......103
Table 6.4 Comparisons of 64-bit Conditional Sum Adder and hybrid Vth scheme Conditional Carry Adders (worst delay case) .....105
Table 6.5 Another comparisons of 64-bit CSA and hybrid Vth scheme Conditional Carry Adders (worst power dissipation case) ...105
Table 6.6 Transistor count comparison of various bit-length comparators .....113


List of Figures
Figure 1.1 Evolution of VLSI .......................................2
Figure 1.2 Propagation delay and power dissipation vs. supply voltage Vdd .....4
Figure 1.3 CMOS inverter and its transfer curve ....................5
Figure 1.4 Short-circuit current of a CMOS inverter during input transition ...5
Figure 1.5 Short channel transistor leakage current mechanisms .....8
Figure 1.6 Estimated leakage power over generations.................9
Figure 1.7 Single-end full-swing logic: (a) CMOS, (b) PTL ..........10
Figure 1.8 CPL Circuit Diagram .....................................11
Figure 1.9 Schematics of NORA ......................................14
Figure 1.10 Schematics of TSPC .....................................14
Figure 1.11 Ripple carry addition rule..............................15
Figure 1.12 Basic carry lookahead adder scheme .....................17
Figure 1.13 4-bit static Manchester carry adder module..............18
Figure 1.14 16-bit carry select adder...............................19
Figure 1.15 Structure of the 16-bit Brent-Kung adder................21
Figure 1.16 Brent-Kung carry-lookahead adder can get a regular layout. Each output wire is a bundle of gi+1 + pi and pi pi+1.....21
Figure 1.17 Structure of the 16-bit Ladner-Fischer adder............22
Figure 1.18 Structure of the 16-bit Kogge-Stone adder...............23
Figure 1.19 Structure of the 16-bit Han-Carlson parallel prefix adder......23
Figure 1.20 Schematic of a 4-bit conditional sum adder..............24

Figure 2.1 Compare CMOS with PTL, a question was raised in the author's mind: "Does any rule exist that contains all good?" .....28
Figure 2.2 (a) K-map of the XOR function. (b) Modified K-map of the XOR Function .........30
Figure 2.3 (a),(b) The original circling procedures of the 2-input XOR modified K-map.....31
Figure 2.4 Priorities of prime implicant patterns are deduced from electrical characteristics .....33,34
Figure 2.5 2-input variables prime implicant patterns' priority...........36
Figure 2.6 The proposed PPIPP successfully gets a mixed logic with minimumgate count......36
Figure 2.7 Using bit field structure to reduce the memory requirement effectively.........37
Figure 2.8 Full swing 2-input XOR functions.(a) The proposed logic style. (b) The DPL structure. (c) The DVL structure. (b) The static CMOS structure......37
Figure 2.9 Function F = Not(A) + B * Not(C) by PPIPP.................38

Figure 3.1 (a) Comparisons of the subthreshold conduction currents of low Vt devices. (b) Low Vt devices with the switch-source impedance (SSI) circuit.....41
Figure 3.2 Schematic diagram of the latched CPL circuit..............42
Figure 3.3 Schematic diagram of the DPL circuit......................42
Figure 3.4 Block diagram of the CSCPTL circuit.......................43
Figure 3.5 Schematic diagram of the CSCPTL circuit...................45
Figure 3.6 HSPICE-simulated timing diagram of the CSCPTL circuit.....47
Figure 3.7 Schematic diagram of the current-sensing buffer of the LCSCPTL circuit.....48
Figure 3.8 HSPICE-simulated timing diagrams of the LCSCPTL and CSCPTL circuits......50
Figure 3.9 Logic trees of the LCSCPTL circuit........................50
Figure 3.10 Layout of the CPL and the LCSCPTL circuits for a two-input AND gate.......51
Figure 3.11 Gates speed comparisons of the CPL, the CSCPTL, the LCSCPTL and the static CMOS circuits...........53
Figure 3.12 Power dissipation comparisons of the CPL, the CSCPTL, the LCSCPTL and the static CMOS circuits.....53
Figure 3.13 Energy consumed for the active mode and idle mode........54

Figure 4.1 Pipeline system..............................56
Figure 4.2 Schematic of TSPC Φ-Sec.....................57
Figure 4.3 Schematic of TSPC ΦB-Sec....................57
Figure 4.4 Schematic of the NSTSPC......................58
Figure 4.5 Schematic of the ANTSPC......................58
Figure 4.6 Number of stacked MOS’s versus the output delay time......63
Figure 4.7 Model of the number of stacked MOS's versus Maximum frequency.....64
Figure 4.8 Max. frequency and power-freq ratio versus number of stacked MOS transistors. The loading is one minimum size inverter......65
Figure 4.9 Max. frequency and power-freq ratio versus number of stacked MOS transistors. The loading is four minimum size inverters....65
Figure 4.10 Max. frequency and power-freq ratio versus supply voltage........65
Figure 4.11 8-bit pipeline CLA architecture. (●: operator, ○: latch) ......66
Figure 4.12 (a) Circuit by NSTSPC for Φ-Sec. (b) Circuit by ANTSPC forΦB-Sec.....66
Figure 4.13 Two-level hierarchical 64-bit CLA architecture............68
Figure 4.14 Test scheme for post-layout simulation....................68
Figure 4.15 2.5V 1.25GHz carry-lookahead adder simulation results.....69

Figure 5.1 Conditional sum addition rules.............................71
Figure 5.2 Schematic and critical delay path of 8-bit conditional sum adder......73
Figure 5.3 The Ware's 8-bit conditional carry adder uses no multiplexer..........74
Figure 5.4 Conditional carry addition rules...........................75
Figure 5.5 After remove the multiplexers for sum output signals in the CSA, the rest multiplexer network only generate C0, C1, C3, and C7.....77
Figure 5.6 Schematic and critical delay path of 8-bit conditional carry adder.....78

Figure 6.1 Layout of the CPL and the LCSCPTL circuits for a two-input AND gate......84
Figure 6.2 Layout of 32-bit Conditional Sum Adder (CSA) using static CMOS (Single-end) logic. [AREA: 920µm × 550µm].......87
Figure 6.3 Layout of 32-bit Conditional Carry Adder (CCA) using static CMOS (Single-end) logic. [AREA: 920µm × 460µm].....87
Figure 6.4 Layout of 32-bit Conditional Sum Adder (CSA) using CPL logic. (Differential-end) [AREA: 905µm × 720µm].........88
Figure 6.5 Layout of 32-bit Conditional Carry Adder (CCA) using CPL logic. (Differential-end) [AREA: 905µm × 550µm].......88
Figure 6.6 Chip photographs of the 32-b Conditional Carry Adder (CCA) using LCSCPL logic. (Differential-end) [AREA: 905µm × 550µm].....89
Figure 6.7 Propagation delay simulation comparison of 32-bit static CMOS CSAs and CCAs.......90
Figure 6.8 Power-delay product simulation comparison of 32-bit static CMOS CSAs and CCAs.....90
Figure 6.9 Propagation delay measurement comparison of 32-bit CSAs andCCAs.........91
Figure 6.10 Power-delay product measurement comparison of 32-bit CSAs and CCAs.....91
Figure 6.11 Propagation delay comparisons of 32-bit CCAs by CPL and LCSCPTL......92
Figure 6.12 8-bit CCA example by pure normal threshold voltage architecture......95
Figure 6.13 8-bit CCA example by normal-medium hybrid 1 architecture.......96
Figure 6.14 8-bit CCA example by normal-medium hybrid 2 architecture.......97
Figure 6.15 8-bit CCA example by normal-medium hybrid 3 architecture.......98
Figure 6.16 8-bit CCA example by normal-medium hybrid 4 architecture.......99
Figure 6.17 8-bit CCA example by normal-medium hybrid 5 architecture.......100
Figure 6.18 8-bit CCA example by normal-medium hybrid 6 architecture.......101
Figure 6.19 8-bit CCA example by pure medium threshold voltage architecture.....102
Figure 6.20 Chip implementation of the 64-bit static CMOS CCA by NM5 hybrid scheme using TSMC 0.25 µm 1p5m+ multi-threshold CMOS process. (Core area: 350µm × 400µm, die size: 539µm × 636µm).....106
Figure 6.21 Compare and swap elements are vital for sorting................108
Figure 6.22 Three-level bitonic sorter.....................................108
Figure 6.23 Classical circuits of integer comparator ......................109
Figure 6.24 Modified 1's complement for comparator design..................110
Figure 6.25 8-bit brief example of the proposed comparator architecture.....112

參考文獻 [1] Neil H.E. Weste and K. Eshraghian, Principle of CMOS VLSI Design: A System Perspective, 2nd Ed. Addison-Wesley, 1993.
[2] A. Bellaouar and M.I. Elmasry, Low-Power Digital VLSI Design: Circuit and Systems. Kluwer Academic publishers, 1995.
[3] J.M. Rabaey and M. Pedram, Low Power Design Methodologies. MA: Kluwer Academic publishers, 1996.
[4] M. Pedram and J.M. Rabaey, Power Aware Design Methodologies. N.Y.: Kluwer Academic publishers, 2002.
[5] M. Anis and M. Elmasry, Multi-Threshold CMOS Digital Circuits — Managing Leakage Power. MA: Kluwer Academic publishers, 2003.
[6] D.E. Knuth, Sorting and Searching. Addison-Wesley, 1973.
[7] K. Hwang, Computer Arithmetic — Principles, Architecture and Design. John Wiley & Sons, 1979.
[8] D.A. Neamen, Semiconductor Physics and Devices. Irwin, 1992.
[9] G. Moore, "Progress in Digital Integrated Circuits," in Proc. International Electron Device Meeting, 1975, pp. 11–13.
[10] M.K. Gowan, L.L. Biro and D.B. Jackson, Digital Equipment Corp., Hudson, MA, USA, "Power considerations in the design of the Alpha 21264 microprocessor," in Proc. 1998 Design Automation Conference, Jun 15-19, 1998, pp.726–731.
[11] S. Thompson, P. Packan, and M. Bohr, "MOS Scaling: Transistor Challenges for the 21st Century," Intel Technology Journal, Q3 1998.
[12] A. Keshavarzi, K. Roy and C. Hawkins, "Intrinsic Leakage in Deep Submicron CMOS ICs — Measurement-Based Test Solutions," IEEE Trans. on VLSI Systems, vol. 8, no. 6, 2000, pp. 717–723.
[13] Z. Chen, L. Wei, A. Keshavarzi and K. Roy, "IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions," IEEE Design and Test of Computers, vol. 19, no. 2, 2002, pp.24–33.
[14] J. Soden, C. Hawkins and A. Miller, "Identifying Defects in Deep-Submicron CMOS ICs," IEEE Spectrum, no. 9, Sep 1996, pp. 66–71.
[15] R.P. Brent and H.-T. Kung, "A Regular Layout for Parallel Adders," IEEE Trans. Computer, vol. C-31, 1982, pp. 280–284.
[16] O.J. Bedrij, "Carry-Select Adder," IRE Transactions on Electronic Computers, vol. EC-11, 1962, pp. 340–346.
[17] R.E. Ladner, M.J. Fischer, "Parallel Prefix Computation," Journal ACM, vol. 27(4), 1980, pp. 831–838.
[18] P. Kogge, H. Stone, "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations," IEEE Trans. Computer, vol. C-22, Aug. 1973, pp.786–793.
[19] T. Han, D.A. Carlson, "Fast Area-efficient VLSI Adders," in Proc. 8th Symp. on Comp. Arithmetic, Sep. 1987, pp. 49–56.
[20] O.L. MacSorley, "High-Speed Arithmetic in Binary Computers," IRE Proceedings, vol. 49, 1961, pp. 67–91.
[21] J. Sklansky, "Conditional-Sum Addition Logic," IRE Trans. Electronic Computers, vol. EC-9, 1960, pp.226–231.
[22] S. Perri, P. Corsonello, and G. Cocorullo, "A High-Speed Energy-Efficient 64-bit Reconfigurable Binary Adder," IEEE Trans. VLSI, vol. 11, no. 5, Oct. 2003, pp. 939–943.
[23] J.-C. Lo, "A Fast Binary Adder with Conditional Carry Generation," IEEE Trans. Computer, vol. 46, no. 2, Feb 1997, pp. 248–253.
[24] Y.-M. Huang and J.B. Kuo, "A High-Speed Conditional Carry Select (CCS) Adder Circuit with a Successively Incremented Carry Number Block (SICNB) Structure for Low-Voltage VLSI Implementation," IEEE Trans. Circuit and System II: Analog & Digital Signal Processing, vol. 47, no. 10, Mar 2000, pp. 1074–1079.
[25] T. Sato, M. Sakate, H. Okada, T. Sukemura and G. Goto, "An 8.5-ns 112-b Transmission Gate Adder with a Conflict-Free Bypass Circuit," IEICE Trans. Electron., Vol.E75-C, No.4, Apr. 1992, pp.555–557.
[26] H. Morinaka, H. Makino, Y. Nakase, H. Suzuki, K. Mashoki and T. Sumi, "A 2.6-ns 64-b Fast and Small CMOS Adder," IEICE Trans. Electron., Vol.E79-C, No.4, Apr. 1996, pp.530–537.
[27] Y. Wang, C. Pai and X. Song, "The Design of Hybrid Carry-Lookahead / Carry-Select Adders," IEEE Trans. Circuit & Systems II: Analog & Digital Signal Processing, vol. 49, no. 1, Jan. 2002, pp. 16–24.
[28] P. Buch, A. Narayan, and A. R. Newton, A. Sangiovanni-Vincentelli, "Logic Synthesis for Large Pass Transistor Circuits," in Proc. Int'l Conf. Computer-Aided Design (ICCAD), 1997, pp. 663 –670.
[29] A.P. Chandrakasan, S. Sheng and R.W. Brodersen, "Low-Power CMOS Digital Design", IEEE J. Solid-State Circuit, vol. 27, no. 4, April 1992, pp. 473 –484.
[30] H. Lee and G.E. Sobelman "New Low-Voltage Circuit for XOR and XNOR," Southeastcon '97 Engineering New Century, Proceeding IEEE, 1997, pp. 225–229.
[31] V.G. Oklobdzija, B. Duchene, "Pass-Transistor Dual Value Logic For Low-Power CMOS," in Proc. 1995 International Symposium on VLSI Technology, Taipei, Taiwan, 1995, pp.341–344.
[32] V.G. Oklobdzija, B. Duchene, "Development and Synthesis Method for Pass-Transistor Logic Family for High-Speed and Low Power CMOS," in Proc. 38th Midwest Symposium, vol. 1, 1996, pp. 298–301.
[33] M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki and Y. Nakagome, "A 1.5 32-b CMOS ALU in Double PASS-Transistor Logic," IEEE J. Solid-State Circuits, vol. 28, no. 11, Nov. 1993, pp. 1145–1151.
[34] J. Wang, S. Fang and W. Feng, "New Efficient Designs for XOR and XNOR Function on the Transistor Level," IEEE J. Solid-State Circuit, vol. 29, July 1995, pp.780–786.
[35] K. Yano, Y. Sasaki, K. Rikino and K. Seki, "Top-Down Pass-transistor Logic Design," IEEE J. Solid-State Circuit, vol. 31, no. 6, June 1996, pp.792–803.
[36] R. Zimmermann and W. Fichtner, "Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic," IEEE J. Solid-State Circuits, vol. 32, July 1997, pp. 1079–1090.
[37] Kuo-Hsing Cheng and Shun-Wen Cheng, "Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization," in Proc. 7th Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2002, pp. 155–159.
[38] A. Chandrakasan and R.W. Brodersen, "Minimizing Power Consumption in Digital CMOS Circuit," Proceedings of the IEEE, vol. 83, no. 4, April 1995, pp. 498–523.
[39] M. Horiguchi, T. Sakata and K. Itoh, "Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI‘s," IEEE J. Solid-State Circuits, vol. 28, Nov. 1993, pp. 1131–1135.
[40] V. von Kaenel, P. Macken and M.G.R. Degrauwe, "A Voltage Reduction Technique for Battery-Operated Systems," IEEE J. Solid-State Circuits, vol. 25, Oct. 1990, pp. 1136–1141.
[41] K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi and A. Shimizu, "A 3.8-ns CMOS 16 ×16-b multiplier using complementary pass-transistor logic," IEEE J. Solid-State Circuits, vol. 25, Apr. 1990, pp. 388–395.
[42] Chung-Yu Wu, J.-H. Lu, and K.-H. Cheng, "A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Application," in Proc. 1995 IEEE Int'l Symp. on Circuits And Systems (ISCAS), Seattle, U.S.A., May 1995, pp. 25–28.
[43] K.-H. Cheng and Y.-Y. Liaw, "A Low Power Current-Sensing Complementary Pass-Transistor Logic (LCSCPTL) for Low-voltage High-Speed Applications," in Proc. 1996 Symposium on VLSI Circuits, Honolulu, Hawaii, U.S.A., June 13-15, 1996, pp.16–17.
[44] Kuo-Hsing Cheng, Shu-Min Chiang, and Shun-Wen Cheng, "The Improvement of Conditional Sum Adder for Low Power Applications," in Proc. IEEE Int'l ASIC Conference, New York, Sep 13-16, 1998, pp. 131-134.
[45] Kuo-Hsing Cheng, Yu-Yee Liow and Shun-Wen Cheng, "1.2V Improved Conditional Sum Adder by Low-Power Current-Sensing Complementary Pass-Transistor Logic," submitted to International Journal of Electronics.
[46] R.H. Karambeck, C.M. Lee, and H.S. Law, "High-Speed Compact Circuits with CMOS," IEEE J. Solid State Circuits, vol. SC-17, June 1982, pp. 614–619.
[47] N.F. Goncalves and H. De Man. "NORA: A Race Free Dynamic CMOS Technique for Pipeline Logic Structures," IEEE J. Solid-State Circuits, vol. SC-18, June 1983, pp. 261–266.
[48] J. Yuan and C. Svensson, "High-Speed CMOS Circuit Technique," IEEE J. Solid-State Circuits, vol. 24, Feb 1989, pp. 62–70.
[49] K. Shimohigashi and K. Seki, "Low-Voltage ULSI Design," IEEE J. Solid-State Circuits, vol. 28, Apr. 1993, pp. 408–413.
[50] C.-G. Huang, "Implementation of True Single-Phase Clock D Flip-Flops," Electronics Letters, vol. 30, Aug. 1994, pp. 1373–1374.
[51] D. Dozza, M. Gaddoni, and G. Baccarani, "A 3.5ns, 64 bit, Carry-Lookahead Adder," in Proc. 1996 IEEE Int'l Symp. on Circuit and Systems, vol. II, June 1996, pp. 297–300.
[52] Kuo-Hsing Cheng and Y.-C. Huang, "The Non-full Voltage Swing TSPC (NSTSPC) Logic Design," in Proc. 2nd IEEE Asia Pacific Conference on ASICs (APASIC), Cheju, Korea, Aug 28-30, 2000, pp.37–40.
[53] Kuo-Hsing Cheng, W.-S. Lee and Y.-C. Huang, "A 1.2V 500MHz 32-bit Carry-Lookahead Adder," in Proc. of the 8th IEEE Int'l Conf. on Electronics, Circuits and Systems (ICECS), Vol. 2, 2001, pp. 765–768.
[54] R.X. Gu, and M.I. Elmasry, "All-N-logic High-speed True Single-Phase Dynamic CMOS logic," IEEE J. Solid-State Circuits, vol. 31, no. 2, Feb.1996, pp. 247–253.
[55] Chung-Yu Wu, Kuo-Hsing Cheng and J.-S. Wang, "Analysis and Design of a new race-free four-phase CMOS logic," IEEE J. Solid-State Circuits, vol. 28, Jan.1993, pp. 18–25.
[56] Kuo-Hsing Cheng, Shun-Wen Cheng and Wen-Shiuan Lee, "64-bit Pipeline Carry Lookahead Adder using ALL-N-Transistor TSPC Logics," submitted to Journal of Circuits, Systems and Computers.
[57] F.A. Ware, Hewlett-Packard Co., "Conditional Carry Techniques for Digital Processors," U.S. Patent No. 4623982, Nov. 18, 1986.
[58] K. Hwang, Computer Arithmetic: Principles, Architecture, and Design, p.81. John Wiley & Sons, 1979.
[59] T.-S. Cheung and K. Asada, "Design of High-Speed High-Density Parallel Adders and Multipliers Using Regenerative Pass-Transistor Logic," IEICE Trans. Electron., Vol.E80-C, No.3, Mar. 1997, pp.478–488.
[60] Kuo-Hsing Cheng and Shun-Wen Cheng, "Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications," Journal of Information Science and Engineering. (Accepted).
[61] D. Takashima, S. Watanabe, H. Nakano, Y. Oowaki, K. Ohuchi and H. Tango, "Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory," IEEE J. Solid-State Circuits, Vol. 29, Apr. 1994, pp.441–447.
[62] H.-J. Yoo, "Dual-VT Self-timed CMOS Logic for Low Subthreshold Current Multigigabit Synchronous DRAM," IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 45, No. 9, Sept. 1998, pp. 1263–1271.
[63] C.-C. Wang, P.-M. Lee and K.-L. Chen, "An SRAM Design Using Dual Threshold Voltage Transistors and Low-power Quenchers," IEEE J. Solid-State Circuits, Vol. 38, Oct. 2003, pp.1712–1720.
[64] N. Shibata, H. Morimura, M. Watanabe, "A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with Charge-Recycling Input/Output Buffers," IEEE J. Solid-State Circuits, Vol. 34, June 1999, pp. 866–877.
[65] V. Kursun and E.G. Friedman, "Sleep Switch Dual Threshold Voltage Domino Logic with Reduced Standby Leakage Current," IEEE Trans. on VLSI Systems, Vol. 12, No. 5, May 2004, pp. 485–496.
[66] J.T. Kao, A.P. Chandrakasan, "Dual-threshold Voltage Techniques for Low-power Digital Circuits," IEEE Journal of Solid-State Circuits, Vol. 35, July 2000, pp. 1009–1018.
[67] L. Wei, Z. Chen, K. Roy, Mark C. Johnson, Y. Ye, and V.K. De, "Design and Optimization of Dual-Threshold Circuits for Low-Voltage Low-Power Applications," IEEE Trans. on VLSI Systems, Vol. 7, No. 1, March 1999, pp. 16–24.
[68] S. Sirichotiyakul, T. Edwards, C. Oh, R. Panda, and D. Blaauw, "Duet: An Accurate Leakage Estimation and Optimization Tool for Dual-Vt Circuits," IEEE Trans. on VLSI Systems, Vol. 10, No. 2, April 2002, pp. 79–90.
[69] P. Pant, R.K. Roy, A. Chattejee, "Dual-threshold Voltage Assignment with Transistor Sizing for Low Power CMOS Circuits," IEEE Trans. on VLSI Systems, Vol. 9, No. 2, April 2002, pp. 390–394.
[70] M.M. Khellah and M.I. Elmasry, "Power Minimization of High-performance Submicron CMOS Circuits Using a Dual-Vdd Dual-Vth (DVDV) Approach," in Proc. Int'l Symp. on Low Power Electronics and Design (ISLPED), 16-17 Aug. 1999, pp. 106–108.
[71] Kuo-Hsing Cheng, Shun-Wen Cheng and Chan-Wei Huang, "64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design," in Proc. of 2004 IEEE Int'l Workshop on System-on-Chip for Real-Time Applications, (IWSOC 2004), Banff, Alberta, Canada, July 19-21, 2004, pp.65–68.
[72] Kuo-Hsing Cheng and Shun-Wen Cheng, "64-bit High-Performance Power-Aware Conditional Carry Adder Design," IEICE Transaction on Electronics, Vol.E88-C, No.6, June 2005, pp.1322–1331.
[73] K.E. Batcher, "Sorting Networks and Their Applications," in Proc. AFIPS 1968 Spring Joint Computer Conference, Apr. 1968, pp. 307–314.
[74] C.-H. Huang and J.-S. Wang, "High-Performance and Power-Efficient CMOS Comparators", IEEE J. Solid-State Circuits, Vol. 38, Feb. 2003, pp. 254–262.
論文使用權限
  • 同意紙本無償授權給館內讀者為學術之目的重製使用,於2010-06-27公開。
  • 同意授權瀏覽/列印電子全文服務,於2015-06-22起公開。


  • 若您有任何疑問,請與我們聯絡!
    圖書館: 請來電 (02)2621-5656 轉 2281 或 來信