隨著生醫電子應用的快速發展，將晶片穿戴或植入人體用以偵測各種生理訊號或是進行藥物釋放以達到居家照護的目的將成為趨勢。由於此類晶片的電源來源為電池、體熱發電或是無線電能量收集電路，因此在其傳輸介面電路設計上最重要的要求為超低功率消耗，以達到延長使用壽命的目的。由於接收器必須長時間維持開啟狀態，因此接收器的功率消耗佔了整體功率消耗的一半以上，因此實現一超低功耗接收器可大幅延長使用時間。
人體通訊(Human Body Communication)是WBAN(Wireless Body Area Network)中的一種通訊方式，把人體當作通道來傳送訊號。無線通訊和醫療的需求增加，IEEE制定了802.15.6此人體通訊標準，與其它IEEE802.15 無線標準相比，該無線通訊技術對人體安全有非常高的要求並且需要好的QoS(Quality of Service)與數據速率與低功耗等。
本論文提出了一種適用於穿戴式裝置的低功耗人體通訊接器電路設計。 該接收器電路架構採用UMC 0.18 µm CMOS製程。應用於穿戴式裝置時，高功率效率可使穿戴式裝置的使用時間大大提高。所提出之接收器電路在僅有162.3μW的功耗下實現了1 Mb/s的最大傳輸速率。因此，可以實現每接收位162.3 pJ的最小能耗。

As age advances, the electronic applications in the biomedical develops rapidly. It is the trend that people carry chips or implant chips into their body in order to detect a variety of physiological signals. Also, they use chips to release medicines to achieve the purpose of home care. As those chip’s power source used for the battery, the power generation of body heat or radio energy harvested circuit, therefore the most important requirements in transmission interface circuit design for ultra-low power consumption to extend the service life of purpose. Since the receiver must remain turn on for a long time, the receiver's power consumption accounted for more than half of the overall power consumption, therefore to achieve an ultra-low power receiver can significantly extend the used time.
Human Body Communication (HBC) is a communication method in Wireless Body Area Network(WBAN), which uses the human body as a channel to transmit signals. The demand for wireless communication and medical care has increased. The IEEE has established the human body communication standard 802.15.6. Compared with other IEEE802.15 wireless standards, the wireless communication technology has required very high for human safety and good Quality of Service(QoS)、data rate and low power consumption.
An low power human body communication (HBC) receiver applied for wearable devices is presented. The receiver is implemented in UMC 0.18 µm CMOS process. As applying for wearable devices, the high power efficiency leads to a great improvement of lift time of the wearable devices. The proposed receiver achieves a maximum data rate of 1 Mb/s under a power consumption of only 162 μW. Thus, minimum energy consumption per received bit of 162 pJ can be achieved.

致謝 I
中文摘要 III
ABSTRACT IV
目錄 VI
圖目錄 IX
表目錄 XIII
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 3
第二章 人體通訊介紹與應用 4
2.1 無線人體區域網路介紹 4
2.2 IEEE 802.15.6之標準規範 4
2.3 人體通訊應用 6
第三章 接收發射器電路系統設計 7
3.1 雙模發射器系統設計 7
3.1.1 Frequency Selective Digital Transmission (FSDT) 8
3.1.2 Narrow Band Digital Transmission (NBDT) 10
3.2 雙模接收器系統設計 11
3.2.1 超低功耗電路設計 13
3.2.2 類比式接收器電路設計 16
3.2.3 全數位式接收器電路設計-時脈與資料回復電路 16
3.3 逐漸逼近式類比數位轉換器 17
3.3.1 二位元搜尋法 19
第四章 接收器發射器電路設計 20
4.1 超低功耗接收器電路設計 20
4.1.1 前端放大器 22
4.1.2 低通濾波器 24
4.1.3 動態比較器 26
4.2 超低功耗接收器電路設計 28
4.2.1 Hogge相位偵測器(Hogge Phase Detector) 29
4.2.2 時間數位轉換器(Time to Digital Converter, TDC) 30
4.2.3 數位低通濾波器(Digital Low-pass Filter, DLPF) 31
4.2.4 數位控制振盪器(Digital Control Oscillator, DCO) 32
4.3 超低功耗接收器電路設計 34
4.3.1 FSDT調變技術 35
4.3.2 NBDT調變技術 37
4.4 通道估測系統設計 37
4.5 逐漸逼近式類比數位轉換器(SAR ADC) 38
4.5.1 雙端電容式數位類比轉換器 42
4.5.2 雙端電容式數位類比轉換器 43
4.5.3 動態比較器(Dynamic Comparator) 44
4.6 電路模擬結果 45
4.6.1 超低功耗接收器前端電路模擬結果 45
4.6.2 FSDT調變技術之發射器電路模擬結果 50
4.6.3 逐漸逼近式類比數位轉換器電路模擬結果 51
4.7 晶片佈局 62
4.7.1 超低功耗接收器電路之佈局圖 62
4.7.2 逐漸逼近式類比數位轉換器電路之佈局圖 64
第五章 電路量測 66
5.1 量測方式 66
5.2 量測結果 67
第六章 結論與未來展望 69
參考文獻(Reference) 70
附錄 76

圖目錄
圖 1.1 人體傳輸通道模擬系統 2
圖 2.1 頻段圖 5
圖 3.1 雙模組發射器電路架構 8
圖 3.2 FSDT之發射訊號Spectrum Mask[3] 9
圖 3.3 FSDT調變之發射器架構[3] 9
圖 3.4 NBDT之發射訊號Spectrum Mask[3] 11
圖 3.5 NBDT調變之發射器架構[3] 11
圖 3.6 半數位類比式雙模接收發射器電路系統 12
圖 3.7 全數位式雙模接收發射器電路系統 13
圖 3.8 (a)電晶體之操作區定義、 (b)0.18 μm電晶體操作在次臨界區，操作速度與其所能提供之本質增益(intrinsic gain)之關係圖。[18] 15
圖 3.9 類比式接收器電路架構設計 16
圖 3.10 時序與資料回復電路架構設計 17
圖 3.11 逐漸逼近式類比數位轉換器 18
圖 3.12 二位元搜尋法 19
圖 4.1 電晶體之ID-VDS特性曲線圖 21
圖 4.2 類比式接收器電路架構 22
圖 4.3 低功耗前端放大器 23
圖 4.4 Sallen-Key低通濾波器 25
圖 4.5 低通Sallen-key濾波器之頻率響應圖 26
圖 4.6動態數位比較器 27
圖 4.7 時序與資料回復電路架構 28
圖 4.8 (a) Hogge PD電路架構 (b) Clock相位領先各點輸出波形 30
圖 4.9 游標尺延遲線之時間數位轉換器之電路與延遲輸出波形 31
圖 4.10 環形振盪器示意圖 33
圖 4.11 數位控制振盪器 34
圖 4.12雙模組發射器電路架構 35
圖 4.13 FSDT人體通訊發射器電路架構 36
圖 4.14 NBDT人體通訊發射器電路架構 37
圖 4.15 指標式通道估測模型圖 38
圖 4.16雙端逐漸逼近式類比數位轉換器電路架構 40
圖 4.17 雙端電容式數位類比轉換器[43] 42
圖 4.18 同步型逐漸逼近式暫存器[47] 43
圖 4.19 動態比較器[48] 44
圖 4.20 前端放大器之時域模擬圖 46
圖 4.21 前端放大器之增益模擬圖 46
圖 4.22 輸入與輸出雜訊模擬圖 46
圖 4.23 二階Sallen-Key 低通濾波器之頻率響應模擬圖 47
圖 4.24 四階Sallen-Key 低通濾波器之頻率響應模擬圖 47
圖 4.25 動態比較器之遲滯曲線圖 48
圖 4.26 超低功耗接收器前端電路之全系統時域模擬圖(tt27) 48
圖 4.27 超低功耗接收器前端電路之全系統時域模擬圖(ff0) 48
圖 4.28 超低功耗接收器前端電路之全系統時域模擬圖(ss75) 49
圖 4.29 FSDT調變之發射器電路設計模擬環境 50
圖 4.30 FSDT調變之發射器電路設計模擬結果 50
圖 4.31 全系統電路之ENOB、SNR與SNDR (tt27) 51
圖 4.32 全系統電路之ENOB、SNR與SNDR (ff0) 52
圖 4.33 全系統電路之ENOB、SNR與SNDR (ss75) 52
圖 4.34 逐漸逼近式類比數位轉換器之全系統時域模擬圖 53
圖 4.35 0V~1.8V之動態比較器時域模擬圖 53
圖 4.36 0V~1.8V之動態比較器遲滯曲線圖 54
圖 4.37 0.3V~1.5V之動態比較器時域模擬圖 54
圖 4.38 0.3V~1.5V之動態比較器遲滯曲線圖 55
圖 4.39 0.8V~1V之動態比較器時域模擬圖 55
圖 4.40 0.8V~1V之動態比較器遲滯曲線圖 56
圖 4.41 0.89V~0.91V之動態比較器時域模擬圖 56
圖 4.42 0.89V~0.91V之動態比較器遲滯曲線圖 57
圖 4.43 0.899V~0.901V之動態比較器時域模擬圖 57
圖 4.44 0.889V~0.901V之動態比較器遲滯曲線圖 58
圖 4.45 雙端電容式數位類比轉換器之時域模擬圖 59
圖 4.46 雙端電容式數位類比轉換器之時域追鎖模擬圖 59
圖 4.47 比較器輸出高電位之SAR邏輯控制電路時域圖 60
圖 4.48 比較器輸出低電位之SAR邏輯控制電路時域圖 60
圖 4.49 超低功耗接收器電路設計之Layout圖 62
圖 4.50 超低功耗接收器電路設計之Layout位置圖 63
圖 4.51 逐漸逼近式類比數位轉換器電路設計之Layout圖 64
圖 4.52 逐漸逼近式類比數位轉換器電路設計之Layout位置圖 65
圖 5.1 晶片量測示意方式 67
圖 5.2 PCB圖 68

表目錄
表 3.1 IEEE 802.15.6 HBC在不同應用下之資料傳輸速率[2] 10
表 4.1 超低功耗接收器電路預期規格表 24
表 4.2 超低功耗接收器電路文獻比較圖 27
表 4.3 時脈與資料回復電路設計預計規格表 29
表 4.4 16-chip Walsh Code Mapping 36
表 4.5 逐漸逼近式類比數位轉換器電路預計規格表 41
表 4.6 輸入震幅與放大器輸出增益(Input 1 dB) 45
表 4.7 超低功耗接收器電路規格表 49
表 4.8 各個輸入振幅下之遲滯曲線圖 58
表 4.9 漸逼近式類比數位轉換器電路規格表 61

[1]VARGA, Virag, et al. , “Designing Groundless Body Channel Communication Systems: Performance and Implications,” Proceedings of  The 31st Annual ACM Symposium on User Interface Software and Technology, p. 683-695, 2018.
[2]Jianqing Wang and Qiong Wang , “Body Area Communications: Channel Modeling, Communication Systems, and EMC,” in Introduction to Body Area Communications, 2013 ed., John Wiley & Sons Singapore Pte. Ltd, 2013, pp 1-18.
[3]Kang, Tae-Wook & Hwang, Jung-Hwan & Kim, Sung-Eun & Oh, Kwang-Il & Park, Hyung-Il & Lim, In-gi & Kang, Sung, “Highly Simplified and Bandwidth-Efficient Human Body Communications Based on IEEE 802.15.6 WBANs Standard.” ETRI Journal.
[4]C. K. Ho, X. Liu and M. Je, "Data rate enhancement method for body channel frequency selective digital transmission scheme," 2013 IEEE MTT-S International Microwave Workshop Series on RF and Wireless Technologies for Biomedical and Healthcare Applications (IMWS-BIO), Singapore, 2013.
[5]S. Maity, D. Das, X. Jiang and S. Sen, "Secure Human-Internet using dynamic Human Body Communication," 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Taipei, 2017.
[6]R. Keyes and T. Watson, "On power dissipation in semiconductor computing elements," Proc. IRE (Corresp.), vol. 50, p. 2485, Dec 1962.
[7]R. M. Swanson and J. D. Meindl, "Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits," IEEE Journal of Solid-State Circuits, vol. 7, no. 2, pp. 146-153, April. 1972.
[8]A. Wang, "An ultra-low voltage FFT processor using energy-aware techniques," Ph.D. dissertation, Massachusetts Institute of Technology, 2003.
[9]B. Calhoun, "Low Energy Digital Circuit Design Using Sub-threshold Operation," Ph.D. dissertation, Massachusetts Institute of Technology, 2005.
[10]A. Cerpa, ,]. Elson, D. Estrin, L. Girod, M. Hamilton, and J. Zhao, "Habitat Monitoring: Application Driver for Wireless Communications Technology," in Proceedings of the ACM SIGCOMM Workshop on Data Communications inLatin America and the Caribbean, 2001, pp. 20-41.
[11]A. Mainwaring, J. Polastre, R. Szewczyk, D. Culler, and J. Anderson, "Wireless Sensor Networks for Habitat Monitoring," in ACM International Workshop onWireless Sensor Networks and Applications (WSNA), 2002, pp. 88-97.
[12]E. Biagioni and K. Bridges, "'The Application of Remote Sensor Technoloy to Assist the Recovery of Rare and Endangered Species," Special Issue onDistributed Sensor Networks for the International Journal of High PerformanceComputing Applications, vol. 16, no. 3, pp. 315-324, Aug. 2002.
[13]L. Schwiebert, S. Gupta, and J. Weinmann, "Research Challenges in Wireless Networks of Biomedical Sensors," in Mobile Computing and Netiuorking, 2001, pp. 151-165.
[14]R. Weinstein, "RFID: a technical overview and its application to the enterprise," IT Professional, vol. 7, no. 3, pp. 27-33, May-June 2005.
[15]Eric Vittoz and Jean Fellrath, "CMOS Analog Integrated Circuits Based on Weak Inversion Operation," IEEE Journal of Solid-State Circuits, vol. 12, no. 3, pp. 224-231, June 1977.
[16]R. Lyon and C Mead, "An analog electronic cochlea," in IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 36, no. 7, July 1988, pp. 1119-1134.
[17]M. Deen, LI. Kazemeini, and S. Nasch, "Ultra-low Power VCOs – Performance Characteristics and Modeling," in IEEE Internationl Caracas Conference on Devices, Circuits and Systems Digest of Technical Papers, Apr. 2002, pp. C033-1 to C033-8.
[18]C. C. Enz, N. Scolari, and U. Yodprasit, "Ultra Low-Power Radio Design for Wireless Sensor Networks," IEEE Int. Workshop on Radio-Frequency Integration Technology, pp. 1-17, Dec. 2005.
[19]H. Shih, C. Chen, Y. Chang and Y. Hu, "An Ultralow Power Multirate FSK Demodulator With Digital-Assisted Calibrated Delay-Line Based Phase Shifter for High-Speed Biomedical Zero-IF Receivers," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 1, pp. 98-106, Jan. 2015.
[20]K. Wang, C. Meng, T. Lo and G. Huang, "0.35-μm SiGe BiCMOS weaver image rejection receiver with 60-GHz double-quadrature sub-harmonic Schottky Diode mixer and 10-GHz double quadrature Gilbert mixer," 2017 IEEE Asia Pacific Microwave Conference (APMC), Kuala Lumpar, 2017.
[21]S. k. gupta, N. yadava and R. K. Chauhan, "Gilbert mixer cell design for RF application using CMOS technology," 2019 IEEE 5th International Conference for Convergence in Technology (I2CT), Bombay, India, 2019.
[22]S. Mehta, X. J. Li and A. Aneja, "A Low Noise Image-Rejection Gilbert Mixer for Software Defined Radios," 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, India, 2020.
[23]U. K. Sharma, A. Chaturvedi and M. Kumar, "A high gain down-conversion mixer in 0.18um CMOS technology for ultra wideband applications," 2016 3rd International Conference on Signal Processing and Integrated Networks (SPIN), Noida, 2016.
[24]G. Kaur, A. Q. Ansari and M. S. Hashmi, "Third Order Sallen key Lowpass Filter in Fractional Domain," 2018 International Conference on Computing, Power and Communication Technologies (GUCON), Greater Noida, Uttar Pradesh, India, 2018.
[25]M. De Matteis, F. Resta, A. Pipino, S. D’Amico and A. Baschirotto, "A 28.8-MHz 23-dBm-IIP3 3.2-mW Sallen-Key Fourth-Order Filter With Out-of-Band Zeros Cancellation," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 12, pp. 1116-1120, Dec. 2016.
[26]D. Webb et al., "Low-Noise, Low-Power Pulse Shaper for Particle Detection (Invited Paper)," 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA, 2020.
[27]L. Rozaqi, A. Nugroho, K. H. Sanjaya and A. Ivonita Simbolon, "Design of Analog and Digital Filter of Electromyography," 2019 International Conference on Sustainable Energy Engineering and Application (ICSEEA), Tangerang, Indonesia, 2019.
[28]M. Li, Y. Lu, C. Yang and C. Lin, "PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems," 2019 International SoC Design Conference (ISOCC), Jeju, Korea (South), 2019.
[29]S. Ghuguloth, S. Todima, S. Pastham, B. P. Kumar and C. S. Paidimarry, "Design of PRN based Octa-rate clock and data recovery circuit using FPGA," 2016 International Conference on Signal and Information Processing (IConSIP), Vishnupuri, 2016.
[30]B. S. Sankalp, N. J. M. Reddy, B. P. Kumar and C. S. Paidimarry, "A novel FPGA based digital octa-rate clock and data recovery circuit," 2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Hyderabad, 2015.
[31]A. M. Zaki, "Adaptive Clock and Data Recovery for Asymmetric Triangular Frequency Modulation Profile," 2019 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), Victoria, BC, Canada, 2019.
[32]S. Guo et al., "A low-voltage low-power 25 Gb/s clock and data recovery with equalizer in 65 nm CMOS," 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Phoenix, AZ, 2015.
[33]L. Tang, W. Gai, L. Shi and X. Xiang, "A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017. 
[34]K. Pyun, D. Kwon and W. Choi, "A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector," 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, 2016.
[35]X. Zhao, Y. Chen, P. Mak and R. P. Martins, "A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS," 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Bangkok, Thailand, 2019.
[36]J. Kang and C. Lee, "Digital clock data recovery circuit fot S/PDIF," 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, 2016.
[37]J. Lin, C. Yang and H. Wu, "A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With $4	imes$ Oversampling," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 4, pp. 791-795, April 2015.
[38]G. Shu, W. Choi and P. K. Hanumolu, "Digital Clock and Data Recovery Circuits for Optical Links," 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Austin, TX, 2016.
[39]S. Mortezapour and E. K. F. Lee, "A 1-V, 8-bit successive approximation ADC in standard CMOS process," in IEEE Journal of Solid-State Circuits, vol. 35, no. 4, pp. 642-646, April 2000, doi: 10.1109/4.839925.
[40]David A.Johns and Ken Martin,”Analog integrated circuit design,”John Wiley & Sons Inc.,1997.
[41]S. Song, N. Cho, S. Kim and H. Yoo, "A 4.8-mW 10-Mb/s Wideband Signaling Receiver Analog Front-End for Human Body Communications," 2006 Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 488-491, doi: 10.1109/ESSCIR.2006.307496.P. Harikumar, M. I. Kazim and J. J. Wikner, "An analog receiver front-end for capacitive body-coupled communication," NORCHIP 2012, 2012, pp. 1-4, doi: 10.1109/NORCHP.2012.6403137.
[42]T. Song, H. Oh, E. Yoon and S. Hong, "A Low-Power 2.4-GHz Current-Reused Receiver Front-End and Frequency Source for Wireless Sensor Network," in IEEE Journal of Solid-State Circuits, vol. 42, no. 5, pp. 1012-1022, May 2007, doi: 10.1109/JSSC.2007.894338.
[43]K.-L. Lin, A. Kemna, and B. J. Hosticka, Modular low-power, high-speed CMOS analog-to-digital converter for embedded systems, Kluwer Academic Publishers, 2003.
[44]Y. Chung, Q. Zeng and Y. Lin, "A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 2, pp. 358-368, Feb. 2020, doi: 10.1109/TCSI.2019.2922726.
[45]E. Youn and Y. Jang, "12-bit 20M-S/s SAR ADC using C-R DAC and Capacitor Calibration," 2018 International SoC Design Conference (ISOCC), Daegu, Korea (South), 2018, pp. 1-2, doi: 10.1109/ISOCC.2018.8649894.
[46]V. P. Singh, G. K. Sharma and A. Shukla, "Power efficient SAR ADC designed in 90 nm CMOS technology," 2017 2nd International Conference on Telecommunication and Networks (TEL-NET), Noida, 2017, pp. 1-5, doi: 10.1109/TEL-NET.2017.8343542.
[47]X. Zou and S. Nakatake, "A Fully Synthesizable, 0.3V, 10nW Rail-to-rail Dynamic Voltage Comparator," 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA, 2020, pp. 199-202, doi: 10.1109/MWSCAS48704.2020.9184498.