高壓製程廣泛地應用在驅動電路(driver circuits)、視訊通訊 (telecommunication)、電源開關(power switch)及汽車面板(motor control system)等等的應用. 在驅動電路技術中，高壓的金氧半場效電晶體通常拿來當做靜電放電的保護元件，除此之外同時還可以當做輸出級的驅動元件(output driver )，由於高壓的操作電壓較高，使得高壓的金氧半場效電晶體之靜電放電能力比低壓的金氧半場效電晶體之靜電放電來的低，因此靜電放電可靠度的問題在高壓金氧半場效電晶體製程中製作的積體電路產品也變的非常重要。
除此之外高壓元件的耐壓能力也是另一考量，增加元件崩潰電壓的方式可改由元件製程上著手，可藉由改變元件的飄移摻雜(drift)的離子植入濃度、劑量，或元件接面的曲度(curvature)、通道長度、製程材料等條件，以便增加元件的崩潰電壓；但以一般IC設計公司而言改變製程條件是不可行的，因此本論文只能利用佈局(layout)參數變化，使得高壓之金氧半場效電晶體有較高的崩潰電壓以及較好的靜電放電防護能力，而且不需增加額外光罩或上述各種改變製程方式。
本論文中，會說明高壓金氧半場效電晶體元件的詳細失效機制(Failure Mechanism)，瞭解其失效機制後針對失效點做改善，目前已有方法有效地使寄生於N型橫向擴散高壓金氧半場效電晶體的載子延緩進入導通狀態，其方法在汲極端下方增加N型坡度摻雜(N-grade)距離，並可有效地增加崩潰電壓，但汲極端接觸點到閘極距離不變，亦不需增加額外光罩，且和晶圓廠所提供的設計規範做比較，在N+內縮之後對靜電放電(ESD)能力及崩潰電壓有何影響及其趨勢。本實驗使用聯華電子0.6微米之30伏特的高壓金氧半場效導體製程。

HV processes are widely applied in driver circuits, power switches, telecommunications, and motor control systems, etc . Among driver circuit technology, HV MOS are usually used to be the ESD protection device  and the driver of output stage. Because of the high operation voltage, the ESD level of HV MOS is lower than LV MOS. Therefore, ESD reliability of IC products is very important when using HV MOS process.
    In addition, the high voltage resistance capability of HV device is another important issue. By modifying the process, there are many ways to improve the breakdown voltage of the devices, such as modification of ion implement concentration, dosage, device interface curvature, channel length, process material, etc. However, to change the conditions of the process is impractical for general IC design houses! In this paper, we can only change the layout parameters to improve the breakdown voltage and ESD level of HV MOS and it doesn’t need to add extra mask layer or do any process changing.
    In the work we’ll describe the detail failure mechanism of HV MOS and do some improvement after understanding the failure mechanism. In the present day, there is an effective way to slow down the carrier that is parasitical in NMOS into conductive mode. The ways efficiently improve breakdown voltage by increasing the N-grade distance under the drain terminal and it doesn’t need to change the DCG distance or add extra mask layer. After comparing with the design rule that is provided by the foundry, we can realize the effects and trend after shrinking the N-plus area. This experience uses UMC 0.6um 30V HV MOS process.

第一章	緒論………………………………………………………...	1
	1.1	研究背景與研究動機	3
	1.2	論文架構	8
			
第二章	靜電放電模式及測試組合	10
	2.1	靜電放電模式	10
	2.1.1	人體放電模式(Human Body Model)	11
	2.1.2	機器放電模式(Machine Model)	12
	2.1.3	元件充電模式 (Charged-Device Model14
	2.2	靜電放電測試組合15
	2.2.1	IO腳位的測試方式15
	2.2.2	IO對IO腳位的測試方式 17
	2.2.3	VDD對VSS腳位的測試方式19
	2.3	靜電放電測試的判定標準21
			
第三章	實驗電路、元件及佈局參數介紹22
	3.1	實驗電路	22
	3.2	實驗元件之參數介紹25
	3.3	佈局參數	27
			
第四章	量測結果與分析	31
	4.1	靜電放電及傳輸線觸波量測結果	36
	4.1.1	GGNMOS架構38
	4.1.2	GCNMOS架構	50
	4.2	失效分析探討57
	4.2.1	雷射光束電阻異常偵測	58
	4.2.2	聚焦式離子束顯微鏡	61
		
第五章	結論與未來展望	65
	5.1	結論	65
	5.2	未來與展望	66

圖1.1	非對稱高壓N型金氧半場效電晶體橫截面結構圖4
圖1.2	汲極下端沒有加入N-drift的高壓NMOS橫截面結構圖4
圖2.1	人體放電模式(2-KV)的放電電流圖11
圖2.2	HBM和MM的比較圖	13
圖2.3	IO腳位的靜電放電測試方式	16
圖2.4	IO對IO腳位的靜電放電測試方式18
圖2.5	VDD對VSS腳位的靜電放電測試方式	20
圖3.1	電源端到地端之靜電放電箝制電路(a)為GGNMOS及(b)為GCNMOS架構……………………………………………………	23
圖3.2	全晶片之靜電放電防護電路示意圖……………………..………	24
圖3.3	非對稱高壓N型金氧半場效電晶體剖面示意圖…………….….	26
圖3.4	汲極下端N型離子植入包裹氧化層之寬度c (a)為設計規範最小值0.7微米 (b)為內縮0.2微米之佈局示意圖………………..	31
圖3.5	多指狀佈局方式(a)2根指狀佈局 (b) 4根指狀佈局…………….	33
圖3.6	4根指狀佈局方式剖面示意圖…………………………………...	33
圖4.1	調變汲極端接觸點到閘極距離之高壓GGNMOS (a) HBM及MM比較 (b)傳輸線觸波量測到的I-V曲線……………..……...	40
圖4.2	調變通道寬度之高壓GGNMOS (a)HBM及MM比較 (b)傳輸線觸波量測到的I-V曲線………………………………...............	43
		
圖4.3	調變汲極下端N型離子植入包裹氧化層寬度之高壓GGNMOS (a)HBM及MM比較 (b)傳輸線觸波量測到的I-V曲線………...	46
圖4.4	多指狀佈局之高壓GGNMOS (a) HBM及MM比較 (b)傳輸線觸波量測到的I-V曲線…………………………………………...	49
圖4.5	調變通道寬度之高壓GCNMOS (a) HBM及MM比較 (b)傳輸線觸波量測到的I-V曲線………………………………...............	
52
圖4.6	調變通道寬度及不同汲極下端N型離子植入包裹氧化層之寬度(c)值之高壓GCNMOS，(a)HBM及MM比較 (b)傳輸線觸波量測到的I-V曲線……………………………………………...	

55
圖4.7	調變汲極下端N型離子植入包裹氧化層之寬度(c)值之高壓GCNMOS HBM比較……………………………………………..	
56
圖4.8	PS-mode靜電放電路徑示意圖…………………………………...	57
圖4.9	由雷射光束電阻異常偵測觀察，在HNS-mode因靜電放電測試後所造成的損傷(a)為電路佈局 (b)在OBIRCH下影像點發生位置圖 (c)為去層的局部放大圖……………………....................	

60
圖4.10	FIB-SEM分析(a) 汲極端損壞點位置(b) FIB-SEM之橫切面圖.	62
		
表3.1	本次論文中GGNMOS之實驗參數DCG值變化…………..……	28
表3.2	本次論文中GGNMOS之實驗參數W值變化……………...……	29
表3.3	本次論文中GGNMOS之實驗參數c值變化…………..……...…	30
表3.4	本次論文中GGNMOS之多指狀佈局實驗參數………..………..	32
表3.5	本次論文中GCNMOS之實驗參數W值變化………..………….	34
表3.6	本次論文中GCNMOS之實驗參數W值及c值變化………..…..	35
表4.1	GGNMOS參數汲極端接觸點到閘極之距離改變靜電放電特性	39
表4.2	GGNMOS參數通道寬度改變之靜電放電特性………..………..	42
表4.3	GGNMOS參數c值改變之靜電放電特性………..……………...	45
表4.4	GGNMOS多指狀佈局改變之靜電放電特性………..…………..	48
表4.5	GCNMOS參數W值改變之靜電放電特性………..……………..	51
表4.6	GCNMOS參數W及c值改變之靜電放電特性………..………...	54
表5.1	GGNMOS靜電放電特性總表………..…………………………..	64
表5.2	GCNMOS靜電放電特性總表………..…………………………..	66

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