隨著無線網路與可攜式電子產品的流行，近年來類比/數位轉換器皆朝著高頻寬、高解析度及低功耗的目標邁進。相較於離散時間架構的類比/數位轉換器，連續時間架構的類比/數位轉換器將擁有較低的功耗，但是複雜的數學計算過程將增加設計難度。而隨著製程不斷的演進，越來越低的供應電壓與越來越嚴重的漏電情形，增加了類比電路設計的困難。因此如何簡化連續時間架構的類比/數位轉換器的設計流程與類比複雜度將成為為本篇論文的目標。
    本篇論文提出了一個新的連續時間類比/數位三角積分調變器(Delta-sigma Modulator)架構，有別於傳統從離散架構轉換至連續時間架構時，必須增加類比補償路徑或重新設計數位濾波器端，新的架構將類比補償路徑移至數位濾波器實現，並且不須重新設計數位濾波器，新的架構將簡化設計所包含的數學運算或類比電路複雜度。
    本論文主要的研究方向為設計一個適用於GSM/WCDMA/WiMAX的連續時間三角積分調變器。其中電路設計的部份，在較低速的操作模式時，將關閉部分電路以達到減少功耗的目標。以TSMC 90nm 1p9m 標準製程來完成前模擬，其工作電壓為1.2V，頻寬分別為100k/2M/10M Hz，取樣頻率為分別為40M/160M/320M Hz，超取樣率為200/40/16。而最大的訊號雜訊失真比分別為85/70/61 dB，功率消耗則分別為4/6.4/15 mW。而在實現部分與後模擬部分，因為考量到電容和電阻的偏異必須增加額外的調整電容，在晶片面積與成本的考量下只實現WiMAX的規格。

With wireless networks and portable electronic products popularized in recent years, the goals of analog-to-digital converter (ADC) are gradually moving into the trend of high bandwidth, high resolution, and low power consumption. To contrast continuous-time (CT) architecture with discrete-time (DT) architecture, the CT architecture consumes less power than that of the DT architecture. Due to the complex derivation of mathematics, it is difficult to design a proper CT architecture. With the evolution of VLSI process technology, both the lower supply voltage and leakage current increase the difficulties of analog circuit design. This thesis tries to simplify the structure of CT ADC and analog part complexity of the design.
    We present a new architecture of CT analog-to-digital delta sigma modulator (DSM) in this thesis. Differing from the traditional method to design a CT DSM from the DT DSM needs to increase analog compensation paths or re-design the digital filters, the new approach uses digital filters to replace the analog compensation paths without re-designing digital filters. The new method simplifies the design procedural and induces the analog circuit complexity.
    This research tries to design a CT DSM for GSM / WCDMA / WiMAX applications. When operating at low speed mode, it will shut down the part of the circuit to save power. The circuit is designed by the TSMC 90nm 1p9m standard process; the supply voltage is 1.2V; bandwidths are 100k/2M/10M Hz; sampling frequencies are 40M/160M/320M Hz; oversampling rates(OSR) are 200/40/16. The greatest signal to noise distortion ratio are 85/70/61 dB, and the power consumptions are 4/6.4/15 mW(pre-simulations). In the implementation and post-simulations, because of the problems of RC-variation must be additional adjustments capacitors, the chip size and cost will increase, we only present WiMAX specifications.

目錄
中文摘要	I
英文摘要	III
內文目錄	V
圖表目錄	IX

第一章  緒論	1
1.1 研究動機	1
1.2 應用	        2
1.3 論文架構	4

第二章  三角積分調變器	5
2.1三角積分調變器簡介	5
2.2一般三角積分調變器架構	8
2.2.1單一迴路架構	8
2.2.2多迴路架構	9

第三章  連續時間三角積分調變器設計	11
3.1轉換DT DSM至CT DSM	        12
3.2轉換DT DSM至CT DSM在MASH架構	16
3.3 MASH架構經由數位補償轉換DT DSM至CT DSM	20

第四章  非理想效應分析	23
4.1 運算放大器之非理想現象	23
4.1.1 有限直流增益與係數偏移	23
4.1.2 有限增益與頻寬乘積	24
4.2 比較器與DAC之非理想現象	27
4.2.1時脈抖動	        27
4.2.2迴授路徑的時間延遲	30
4.2.3比較器的磁滯現象	36

第五章  系統設與電路設計	 37
5.1 系統設計與模擬結果	 37
5.1.1運算放大器之非理想模擬	 42
5.1.2比較器與DAC之非理想現象 46
5.2 電路實現與前模擬結果	 48
5.2.1運算放大器	48
5.2.2共模迴授電路	51
5.2.3比較器	52
5.2.4電流型式DAC	53
5.2.5偏壓電路	54
5.2.6各級積分器	54
5.3 佈局與後模擬	58

第六章  結論	59
6.1結論	        59
6.2量測考量	64

參考文獻	65

圖目錄

圖1.1通信系統整併演進與擴增的情勢	3
圖2.1三角積分調變器區塊圖	5
圖2.2三角積分調變器基本架構	6
圖2.3三角積分器線性化模型	7
圖2.4 (a)CIFB (b)CIFF架構DSM	9
圖2.5 MASH架構	9
圖3.1 CT DSM與DT DSM開迴路模型	13
圖3.2 DT MASH 2-1-1 DSM	16
圖3.3使用類比補償路徑CT MASH 2-1-1 DSM	19
圖3.4使用原本DT DSM數位濾波器之CT DSM	20
圖3.5將類比補償路徑用數位補償實現之CT DSM	21
圖4.1有限直流增益RC積分器	23
圖4.2 (a)考量次極點與增益誤差的二階DSM(b)修改之後的模型(c)最終        的有限頻寬等效模型	26
圖4.3使用NRZ單一位元量化器時脈抖動的誤差	28
圖4.4使用不同型式迴授波型產生時脈抖動之情形	29
圖4.5使用NRZ發生迴授延遲的情形(A)理想波型(B)發生延遲	30
圖4.6使用RZ發生迴授延遲的情形(A)理想波型(B)發生延遲	30
圖4.7經過標準化發生迴授延遲的波形	31
圖4.8傳統補償迴路延遲方法	32
圖4.9使用數位微分路徑補償迴路延遲方法	33
圖4.10利用數位補償方法	34
圖4.11使用PI-element元件補償迴路延遲方法	34
圖4.12 PI-elemenT電路	35
圖5.1 DT MASH 2-1-1包含係數之DSM	37
圖5.2 DT MASH 2-1-1之動態範圍	38
圖5.3考慮迴路延遲時間使用類比補償之CT MASH 2-1-1 DSM	39
圖5.4考慮迴路延遲時間使用類比補償之CT MASH 2-1-1 DSM動態範圍	40
圖5.5考慮迴路延遲時間使用數位補償之CT MASH 2-1-1 DSM	41
圖5.6考慮迴路延遲時間使用數位補償之CT MASH 2-1-1 DSM動態範圍	41
圖5.7使用Verilog-A有限直流增益OPAMP模擬結果	43
圖5.8使用Verilog-A有限增益與頻寬乘積OPAMP模擬結果	44
圖5.9電容電阻飄移模擬結果	45
圖5.10時脈抖動對於WiMAX系統效能影響	46
圖5.11迴路延遲時間對於WiMAX系統效能影響	47
圖5.12比較器磁滯大小對於WiMAX系統效能影響	47
圖5.13整體電路圖	48
圖5.14 NMOS輸入對的串接型運算放大器	49
圖5.15 WiMAX模式時第一二級運算放大器波德圖(a)TT (b)FF(c) SS	50
圖5.16運算放大器開迴路差動訊號放大模擬	51 
圖5.17連續時間共模迴授電路	52
圖5.18比較器電路	52
圖5.19比較器磁滯模擬	53
圖5.20電流型式DAC	53
圖5.21 (a)運算放大器偏壓電路(b)DAC偏壓電路	54
圖5.22 (a)第一級RC積分器架構(b)使用PI-ELEMENT積分器架構	55
圖5.23 在TT 25℃時(a)WiMAX (b)WCDMA(c)GSM模式的頻譜	57
圖5.24 考量電容電阻飄移的可調整之WIMAX規格系統	58
圖5.25 系統佈局圖	60
圖6.1  量測考量	64

表目錄

表1.1 各系統所需規格	3
表3.1 不同補償方式的比較	22
表4.1 四種補償方式的比較	36
表5.1 DT MASH 2-1-1之模擬結果	38
表5.2使用數位補償之CT MASH 2-1-1 DSM模擬結果	42
表5.3各級運算放大器規格	45
表5.4各級運算放大器在不同模式與不同Corner的模擬結果	50
表5.5系統在不同Corner及溫度模擬結果	56
表5.6運算放大器之前後模擬比較	59
表5.7比較器之前後模擬比較	59
表5.8預期規格	61
表5.9 FOM比較表	62

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