系統晶片會隨著製程、供應電壓定與溫度偏異而產生飄移，電路上會產生非理想的偏異，會造成系統上的不穩定，進而造成晶片的不正常工作，更嚴重而導致晶片的損壞，如何設計出一不隨製程、電壓變異且低功率消耗的穩壓器便是研究中一個重要的議題，在電路設計上使用數位電路才取代誤差放大器，因此，此論文目標為改良之前學長所設計出一個使用連續漸近式類比數位轉換器架構之低壓降線性穩壓器。
低壓降線性穩壓器有幾項主要考量的特性參數: (1) 輸出電壓差(△V)與靜態電流(Quiescent Current, Iq) (2) 線性調節率(Line Regulation, LNR) (3)負載調節率(Load Regulation, LDR)；這些參數都與負載電流、精準度、穩壓時間有著密不可分的關係。整體電路可分為三大部分，第一部分為利用8位元連續漸近式類比數位轉換器架構，第二部分為製程變異，而第三部分為智控機制。
    低壓降線性穩壓器電路的設計，產生一電壓正負誤差10%的電壓與一最低與最高的可承受電流，而這兩電壓與電流經由功率電晶體後，最後輸出還能穩定在固定的電壓，利用連續漸近式類比數位轉換器的訊號來控制功率電晶體以達到穩定的輸出電壓，並且降低在穩態中，所消耗的靜態電流。首先利用製程變異偵測在哪個製成，第二利用比較器來比較輸入電壓與偵測負載來判斷所要增加的電壓給予回授電壓。最後第三點，在設計連續漸近式類比數位轉換器架構和比較器部分，盡量降低DC電流消耗以節省整體的電流消耗。

SoC circuits may produce non-ideal effects due to variations of process, supply voltage, and temperature, which cause the chip not to work or lead to damage the chip in serious. Besides, how to design a low power consumption of the circuit is an important issue. In this thesis, we will design a low dropout (LDO) regulator circuit that uses a successive approximation analog to digital converter to replace the error amplifier.
There are several key considerations for low dropout linear regulator characteristic parameters, such as: output voltage difference (ΔV), quiescent current (Iq), linear regulation rate (LNR), and load regulation rate (LDR). These parameters have close relationship with the load current, precision, and settling time of the LDO. The proposed LDO circuit consists of three parts: an 8-bit successive approximation analog-to-digital converter (ADC), a process variation adjuster, and a scanner to scan Vin and the output resistance. The proposed LDO uses the signal from the SAR ADC to control the power transistor to adapt the output voltage and can reduce the quiescent current in the steady state. During the operation, firstly it adjusts the process variation. Secondly, it compares the input voltage and the resistance to control the feedback additive voltage value to the feedback voltage to turn on or turn off the power transistors. Finally, the designed comparators may reduce the DC current.

目錄
第一章  緒論	...1
1.1	研究背景與動機	1
1.2	設計流程與應用	2
1.3	論文架構	5
第二章  低壓降線性穩壓器	6
2.1	低壓降線性穩壓器概論	6
2.2	低壓降線性穩壓器之特性參數	8
2.2.1	輸出電壓差(Dropout Voltage)與靜態電流(Quiescent Current)	8
2.2.2	線性調節率(Line Regulation, LNR)與負載調節率(Load Regulation, LDR)	10
2.3	數位式低壓降線性穩壓器	13
2.4	文獻回顧與探討	13
2.4.1	應用於40nm製程具快速暫態響應之數位LDO [14]	13
2.4.2	串列輸入並列輸出雙向移位暫存器 [15]	14
2.4.3	具數位式控制器之電壓線性穩壓器 [16]	15
第三章 類比數位轉換器的基本原理與架構分析	18
3.1	類比數位轉換器架構介紹與分析	18
3.1.1	快閃式類比數位轉換器（Flash or Parallel ADC）	18
3.1.2	管線式類比數位轉換器（Pipeline ADC）	20
3.1.3	積分式類比數位轉換器（Integrating ADC）	21
3.1.4	連續漸近式類比數位轉換器（SAR ADC）	21
3.1.5	二位元搜尋演算法（Binary search algorithm）	22
3.2	類比數位轉換器基本原理	25
3.2.1	解析度（Resolution）	25
3.2.2	最小有效位元（Least Significant Bit, LSB）	26
3.2.3	量化誤差（Quantization Error）	27
3.2.4	缺碼（Missing Code）	28
3.2.5	微分非線性誤差（Differential Non-Linearity, DNL）	28
3.2.6	積分非線性誤差（Integral Non-Linearity, INL）	28
3.2.7	信號雜訊比（Signal to Noise Ratio, SNR）	29
3.2.8	有效位元（Effective Number of Bits, ENOB）	30
3.2.9	高取樣定理（Over-Sampling Method）	31
3.3	數位類比轉換器電路設計（DAC）	33
3.3.1	二位元加權電阻式數位類比轉換器（Binary Weighted Resistor）	33
3.3.2	R-2R 階梯式數位類比轉換器（R-2R Ladder Resistor）	34
3.3.3	電容式數位類比轉換器 (Charge-Redistribution)	35
3.4	規格制定	36
第四章  連續漸近式類比數位轉換器與容忍製程變異電路架構	38
4.1	連續漸近式類比數位轉換器基本架構	38
4.2	追蹤保持電路	39
4.2.1	取樣NMOS開關	40
4.2.2	取樣CMOS開關（Complementary Transmission Switch）	41
4.3	比較器電路設計	42
4.4	連續漸近暫存式控制器之電路設計	43
4.5	數位類比轉換器架構（DAC）	47
4.6	容忍製程變異電路架構	49
第五章  連續漸近式類比數位轉換器之低壓降線性穩壓器	51
5.1	數位式低壓降線性穩壓器設計	51
5.2	自動偵測輸入電壓變化與負載變化機制	52
5.1	輸入偵測(VIN Scanner)	53
5.2	輕重載偵測(Resistance Scanner)	53
5.3	帶差電源(Bandgap References Circuit)與電容加法器(Capacitance Adder) 		55
5.3.1	帶差電源(Bandgap References Circuit)	56
5.3.2	電容加法器(Capacitance Adder)[33~34]	57
5.4	連續漸近式類比數位轉換器架構	58
5.4.1	比較器(Comparator)	58
5.4.2	連續漸近式類比數位轉換器操作原理	59
5.5	電路模擬與佈局	60
第六章  結論	86
6.1	結論與未來展望	86
參考文獻 (References)	87

 
圖目錄
圖1.1 晶片設計流程圖	4
圖2.1 傳統低壓降線性穩壓器之電路圖	7
圖2.2 低壓降線性穩壓器之輸入/輸出電壓曲線圖	9
圖2.3 靜態電流示意圖	10
圖2.4 低壓降線性穩壓器之線性調節率示意圖	11
圖2.5 負載調節率示意圖	12
圖2.6快速暫態響應之數位LDO	14
圖2.7串列輸入並列輸出雙向移位暫存器	15
圖2.8數位式控制器之電壓線性穩壓器	16
圖3.1快閃式類比數位轉換器架構圖	19
圖3.2管線式類比數位轉換器	20
圖3.3積分式類比數位轉換器	21
圖3.4連續漸近式類比數位轉換器	22
圖3.5數位類比轉換器輸出電壓變化圖	23
圖3.6 SAR ADC轉換流程圖	24
圖3.7類比數位轉換器資料轉換過程	25
圖3.8理想的3位元ADC類比數位轉換關係	26
圖3.9轉換特性	27
圖3.10 ADC之量化誤差	27
圖3.11 INL、DNL示意圖	29
圖3.12量化雜訊功率頻譜密度圖	32
圖3.13二元加權電阻式數位類比轉換器	33
圖3.14 R-2R階梯式數位類比轉換器	35
圖3.15電容式數位類比轉換器	36
圖4.1 連續漸近式類比數位轉換器方塊圖	38
圖4.2取樣NMOS開關	40
圖4.3 CMOS互補式開關	41
圖4.4電荷注入效應	42
圖4.5使用PMOS和NMOS雙輸入比較器	43
圖4.6一般連續漸近式暫存控制器	44
圖4.7  Non-redundant Successive Approximation Register架構	45
圖4.8 N-th Flip-Flops 方塊圖	46
圖4.9電容式數位類比轉換器	48
圖4.10容忍製程變異電路架構	49
圖5.1連續漸近式類比數位轉換器之低壓降線性穩壓器	52
圖5.2輸入偵測電路圖	53
圖5.3輕重載偵測電路圖	55
圖5.4 PTAT電路架構	57
圖5.5 電容加法器架構	58
圖5.6 連續漸進是類比數位轉換器	60
圖5.7(a)重載穩態模擬結果(TT)	62
圖5.7(b)重載穩態模擬結果(FF)	63
圖5.7(c)重載穩態模擬結果(SS)	63
圖5.8(a)輕載穩態模擬結果(TT)	64
圖5.8(b)輕載穩態模擬結果(FF)	64
圖5.8(c)輕載穩態模擬結果(SS)	65
圖5.9(a)線性調節率模擬圖(TT)	66
圖5.9(b)線性調節率模擬圖(FF)	66
圖5.9(c)線性調節率模擬圖(SS)	67
圖5.10(a)線性調節率模擬圖(TT)	68
圖5.10(b)線性調節率模擬圖(FF)	68
圖5.10(c)線性調節率模擬圖(SS)	69
圖5.11(a)負載調節率模擬圖(TT)	70
圖5.11(b)負載調節率模擬圖(FF)	70
圖5.11(c)負載調節率模擬圖(SS)	71
圖5.12 電路佈局圖	72
圖5.13電路佈局示意圖	72
圖5.14(a)比較器遲滯(TT)遲滯為3.1047mV	73
圖5.14(b)比較器遲滯(FF)遲滯為3.1047mV	73
圖5.14(c)比較器遲滯遲滯為3.41468mV	74
圖5.15(a)重載穩態模擬結果(TT)	75
圖5.15(b)重載穩態模擬結果(FF)	75
圖5.15(c)重載穩態模擬結果(SS)	76
圖5.16(a)輕載穩態模擬結果(TT)	77
圖5.16(b)輕載穩態模擬結果(FF)	78
圖5.16(c)輕載穩態模擬結果(SS)	78
圖5.17(a)線性調節率模擬圖(TT)	79
圖5.17(b)線性調節率模擬圖(FF)	80
圖5.17(c)線性調節率模擬圖(SS)	80
圖5.18(a)線性調節率模擬圖(TT)	81
圖5.18(b)線性調節率模擬圖(FF)	82
圖5.18(c)線性調節率模擬圖(SS)	82
圖5.19(a)負載調節率模擬圖(TT)	83
圖5.19(b)負載調節率模擬圖(FF)	83
圖5.19(c)負載調節率模擬圖(SS)	84
 
 
 
表目錄
表1.1 傳統線性穩壓器與數位式穩壓器之特性	2
表2.1 文獻比較表	17
表3.1類比數位轉換器架構分析	18
表3.2 規格與文獻比較表	37
表4.1八位元連續漸近式控制器執行動作順序	47
表5.1 預計規格表	61
表5.2 specification & post-layout simulation results	71
表5.3 Specification, pre-sim.與post-sim.比較結果	85

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