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中文論文名稱 具寬動態範圍和對數響應輸出之線性數位像素
英文論文名稱 The Design of a Linear Digital Pixel Sensor with Wide Dynamic Range and Logarithmic Response
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士在職專班
系所名稱(英) Department of Electrical Engineering
學年度 94
學期 2
出版年 95
研究生中文姓名 鄒明杰
研究生英文姓名 Ming-Chieh Tsou
學號 792350216
學位類別 碩士
語文別 英文
口試日期 2006-05-21
論文頁數 38頁
口試委員 指導教授-余 繁
共同指導教授-李揚漢
委員-蘇木春
委員-陳建中
委員-余 繁
委員-李揚漢
委員-楊清淵
中文關鍵字 Digital Pixel Sensor (DPS)  Analog-to-Digital converter (ADC)  Fixed Pattern Noise (FPN)  Gray Code  Correlated Double Sampling (CDS)  Passive Pixel Sensor (PPS)  Active Pixel Sensor (APS) 
英文關鍵字 Digital Pixel Sensor (DPS)  Analog-to-Digital converter (ADC)  Fixed Pattern Noise (FPN)  Gray Code  Correlated Double Sampling (CDS)  Passive Pixel Sensor (PPS)  Active Pixel Sensor (APS) 
學科別分類 學科別應用科學電機及電子
中文摘要 一種具有線性排列的數位化像素感應器(DPS),並且具有寬動態範圍和對數響應的設計,使用標準0.5u 的邏輯COMS標準製程來實現。
數位化的像素感測器(DPS)包含了光二極體,放大器,比較器,8位元動態記憶體,一非線性斜坡訊號產生器。利用非線性斜坡訊號產生器可使類比訊號轉換成數位訊號時,能夠傭有全部的動態範圍和多重解析度的轉換(GAMMA的轉換)
英文摘要 A linear Digital Pixel Sensor (DPS) with wide dynamic range and logarithmic response designed in standard 0.5-um CMOS logic process is presented. The Digital Pixel Sensor (DPS) includes a photo diode with capacitive trans-impedance amplifier, a comparator, a 8bit dynamic memory, a non-linear ramp generator. With a nonlinear ramp generator it allows the Analog-to-Digital converter operating in its full dynamic range and also enables the implementation of the ADC in multi-resolution mode.
論文目次 Table of Contents

CHAPTER 1 INTRODUCTION………………………..1

1.1 Current Status of CMOS Sensor …..………………….1
1.2 Digital Pixel Sensor …………………..........................1
1.3 DPS IN LINEAR SENSOR.……………………………….2
1.4 Improvement of DPS ……………………………………...2

CHAPTER 2 CIRCUIT IMPLEMENTATION………..3

2.1 Overview of DPS Chip Architecture……………………3
2.2 CIRCUIT DESIGN……………………..……………………4
2.2.1 Design of Pixel circuit…………….………………4
2.2.1.1 Analysis of Digital Pixel Sensor………………5
2.2.1.2 Simulation Results………………….……………..7
2.2.1.3 Comparator………………………………………….7
2.2.1.4 Simulation on of Comparator Operation………….8
2.2.1.5 8 bit memory……………………..…………………9
2.2.2 Timing Control Generator……………..……………10
2.2.3 Eight Bit Gray Code Counter……………….………11
2.2.4 Bias Generator……………………………..…………13
2.2.4.1 Bias Generate Circuit…………………..………..13
2.2.4.2 Simulation of Bias generation…………..……….13
2.2.5 Ramp Generator………………………………………..14
2.3 Chip Layout of DPS………………….………………………15

CHAPTER 3 LOGARITHMIC RESPONSE OF IMAGE SIGNAL……………….…………………17

3.1 Response of Human Vision………………………………….17
3.2 Why It Needs Logarithmic Conversion
(Gamma Correction )?.................................................................17
3.3 Logarithmic Conversion in DSP…………………….…………19
3.3.1 Sensor with Logarithmic Response…………….………….19
3.3.2 Logarithmic signal output in DPS……………..………...19
3.3.2.1 Non-linear Ramp Generator………...............……….21
3.3.2.2 Fully Dynamic Range Control with Non-linear Ramp Generator………………………….………………21
3.3.3 Non-linear Ramp VS. Linear Ramp in DPS……………..22

CHAPTER 4 TESTING AND CHARACTERIAZTION…....24

4.1 Test Setup………………………………………………...24
4.1.1 Measuring system………………………………….………24
4.1.2 Data Capture and Calculator………………………..……...25
4.2 Electrical and Optical Characterizations………………26
4.2.1 Dynamic Range…………………….………..…………...26
4.2.2 Quantum Efficiency………………………..………………29
4.3 Chip Performance…………………………………….………..29
4.3.1 Uniformity……………………………………………..…..30
4.3.2 Random Noise……………………………………………31
4.3.3 Data Rate…………………………………………………32
4.4 Temporal noise and fixed pattern noise………………………..33

CHAPTER 5 CONCLUSION AND FUTURE WORK…..36

5.1 CONCLUSION……………………………….……………….36
5.2 FUTURE WORK…………………………………..………….36

REFERENCE……………………………………..38

List of Figures
Figure 2.1 BLOCK DIAGRAM of DPS………..…………………...3
Figure 2.2 Circuit design of Digital Pixel…………..……….………4
Figure 2.3 Block diagram and small-signal model of the CTIA
input…………………………………..……………….6
Figure 2.4 Simulated CTIA Output………………….……………..7
Figure 2.5 Comparator circuit……………………………..………..8
Figure 2.6 Simulated Dynamic Range of Comparator……………...9
Figure 2.7 8 bit memory circuit…………………………………….10
Figure 2.8 DPS timing control chart………………………………11
Figure 2.9 Schematic Diagram to Generate Gray Code……………12
Figure 2.10 Comparison Between Gray Code and the Binary
Code…………………………………….……………12
Figure 2.11 Bias Generator Circuit………………………………..13
Figure 2.12 Simulated Bias Generation……………….……………14
Figure 2.13 Schematic Diagram of Ramp Generator……………….15
Figure 2.14 Whole Chip Layout of DPS…………………………...15
Figure 2.15 Cell Layout of DPS…………………………..………...16
Figure 3.1 Gamma curve………………............................................18
Figure 3.2 Pictures with Gamma Correction…………………........18
Figure 3.3 Linear and non-linear ramp signals………….…………20
Figure 3.4 Logarithmic response of a 24pixels output…………….20
Figure 3.5 Non-linear ramp generator circuit……………………….21
Figure 3.6 Simulation Result of the Control of Non-Linear Dynamic

Range……………………………..……………..…….22
Figure 3.7 Simulated Ramp Signal with Capacitively
Load……………………………………………………23
Figure 4.1 Block Diagram of Test System……………………..…...24
Figure 4.2 Photo of the Measuring System…………………………25
Figure 4.3 Data capture and calculator system……………………..26
Figure 4.4 Dark signal output……………………………….……...27
Figure 4.5 Linear signal output………………………….………….28
Figure 4.6 saturated signal output…………………..……………….28
Figure 4.7 Quantum efficiency of photo diode………………..…….29
Figure 4.8 640 pixels digital output………………………………..30
Figure 4.9 640 pixel digital data……....................................……...31
Figure 4.10 Distribution of random noise……………………….…32
Figure 4.11 Digital data waveform………………………………..33
Figure 4.12 DPS scanned picture in 8MHz………………………....33
Figure 4.13 640 pixels data without using CDS…………………….34
Figure 4.14 640 pixels data with CDS technique
implemented…………………………………………..35

List of Tables
Table 4.1 Measure result…………………………………..………27
參考文獻 [1] R. Gregorian, “Introduction to CMOS Op-Amps and Comparators,” New York: Wiley, 1999.
[2] S. Kleinfelder, S. H. Lim, X. Q. Liu, and El. Gamal, “A 10 000 frames/s 0.18 μm CMOS digital pixel sensor with pixel-level memory,” in Proc. ISSCC, 2001, pp. 88–89.
[3] Storm, G.G., Hurwitz, J.E.D., Renshaw, D., Findlater, K.M., Henderson, R.K., Purcell, M.D., “Combined linear-logarithmic CMOS image sensor” Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC, 2004 IEEE International 15-19 Feb. Vol. 1, 2004 pp. 116 - 517
[4] Kitchen, A.; Bouzerdoum, A.; Bermak, A., “Time domain analogue to digital conversion in a digital pixel sensor array,” Electronic Design, Test and Applications, 2004. DELTA 2004. Second IEEE International Workshop on 28-30 Jan, 2004 pp. 108 - 112
[5] Kitchen, A.; Bermak, A.; Bouzerdoum, A., “ PWM digital pixel sensor based on asynchronous self-resetting scheme,” Electron Device Letters, IEEE, Vol. 25, Issue 7, July 2004 , pp. 471 – 473
[6] Kleinfelder, S.; Yandong Chen; Kwiatkowski, K.; Shah, A., “High-speed CMOS image sensor circuits with in situ frame storage,” Nuclear Science, IEEE Transactions on, Vol. 51, Issue 4, Part 1, Aug. 2004, pp. 1648 – 165
[7] Tongprasit, B.; Ito, K.; Shibata, T., “ A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering,” Circuits and Systems, ISCAS 2005. IEEE International Symposium on 23-26, Vol. 3, May 2005, pp. 2389 - 2392

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