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中文論文名稱 使用新型種子值重設技巧之超大型積體電路假性隨機測試法
英文論文名稱 A Novel Reseeding Mechanism for Pseudo-Random Testing of VLSI Circuits
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 93
學期 2
出版年 94
研究生中文姓名 何應甫
研究生英文姓名 Ying-Fu Ho
學號 692390767
學位類別 碩士
語文別 英文
口試日期 2005-06-11
論文頁數 58頁
口試委員 指導教授-饒建奇
委員-陳竹一
委員-李建模
中文關鍵字 內建自我測試  假性隨機測試向量  重設種子值  測試長度  單一定值錯誤  錯誤函蓋率 
英文關鍵字 BIST  Pseudo-Random pattern  reseed  test length  single stuck-at fault  fault coverage 
學科別分類 學科別應用科學電機及電子
中文摘要 近代的設計與封裝技術快速發展,已使得單晶片系(System-On-a-Chip,SoC)成為一個趨勢,由於它是將整個系統所能執行的功能都由一矽晶片來實現,以至於要從外部來測試系統有沒有發生錯誤和缺陷變的非常困難了。所以大部份的設計者在設計晶片的過程中就會將測試的電路也一並加入,也就是所謂的可測試設計(Design for Testability,DFT)。內建自我測試(Built-In Self-Test,BIST)是屬於可測試設計(DFT)的其中一種方法。在BIST的架構裡包含了測試結果壓縮器(response components),信號分析器(signature analyzer),測試向量產生器(test pattern generator,TPG), 在此我們所使用的是線性回溯移位暫存器(Linear Feedback Shift Register,LFSR)。
但是,由線性回溯移位暫存器所產生的測試向量,可能無法得到較高的錯誤涵蓋率(Fault Coverage), 而且,一些無效的測試向量(useless pattern)也會使得測試時間(test time)變長,因為我們使用了重新設定種子值(Reseeding)的技巧,修正測試向量的某些Bits(modify pseudo-random bit),和一個額外加入的計算器,來將錯誤涵蓋率提升到趨近於100%,並同時將測試長度(test length)縮短,亦即測試時間(test time)降低。
重新設定種子值(Reseeding)的方法主要是拿來跳過沒有用的測試向量(useless pattern),以縮短測試的時間。修正測試向量的某些Bits(modify pseudo-random bits)的方法是當無效的測試向量(指無法偵測到錯誤的測試向量)要傳遞到掃描鏈的時候,經由修改數個bits後,變成有用的測試向量(useful pattern),以縮短測試時間和增加錯誤涵蓋率。額外的計數器則是用來計數在何時有用的測試向量值會正好傳遞到掃描鏈(Scan Chain)上,而去捉取他的輸出值以降低測試時間。結合以上三種方法可以將錯誤涵蓋率有效的提升和縮短測試所需的時間。
英文摘要 During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault (useless patterns). In order to reduce the test time, we can remove useless patterns or change from them to useful patterns (fault dropping). In this paper, we reseed, modify the pseudo-random and use an additional bit counter to improve test length and achieve high fault coverage. The fact that a random test set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we pick out number of different less bit, leading to very short test length. And We can use an additional bit counter to control the scan enable signal for capturing (when the useful pattern is loaded into the scan chains). The technique we present is applicable for single-stuck-at faults. The seeds we use are deterministic so 100% faults coverage can be achieved.
Modern design and package technologies make external testing increasingly difficult and the built-in self-test (BIST) has emerged as a promising solution to the VLSI testing problem. BIST is a design for testability methodology aimed at detecting faulty components in a system by incorporating test logic on-chip. The main components of a BIST scheme are the test pattern generator (TPG), the response compactor, and the signature analyzer. The test generator applies a sequence of patterns to the circuit under test (CUT), the responses are compacted into a signature by the response compactor, and the signature is compared to a fault-free reference value.
In this paper, we used an additional bit counter to control the scan enable signal. When the counter achieve to zero, it means that the useful pattern is loaded to the scan chain, so we can disable the scan enable signal for capturing. We pay the price in hardware overhead in order to decrease test length.
論文目次 中文摘要 ……………………………………………………………I
英文摘要 …………………………………………………………III
致謝 …………………………………………………………………V
Table of Contents ………………………………………………VI
List of Figures ………………………………………………VIII
List of Tables ……………………………………………………X
Chapter 1 INTRODUCTION …………………………………………1
1-1 Motivation ……………………………………………………4
1-2 Thesis Overview………………………………………………5
Chapter 2 BASIC CONCEPTS ………………………………………6
2-1 Faults …………………………………………………………6
2.1.1 Circuit Defects and Faults ……………………………7
2.1.2 Fault Detection …………………………………………10
2-2 Fault Simulation……………………………………………14
2.2.1 Serial Fault Simulation ………………………………16
2.2.2 Parallel Fault Simulation ……………………………17
2-3 Seed Calculation……………………………………………19
2-4 Built-In Self Test ……………………………………… 21
2.4.1 BIST Pattern Generation ………………………………21
2.4.2 Test Pattern Generation for BIST ………………… 23
2.4.3 Test-Per-Clock BIST Systems …………………………27
2.4.4 Test-Per-Scan BIST Systems ………………………… 28
Chapter 3 PREVIOUS BIST METHODOLOGIES ……………………32
3-1 Transformed Patterns For BIST …………………………32
3-2 Circuit Partitioning for BIST …………………………36
3-3 Built-In Reseeding For BIST ……………………………38
3-4 Modifying-Bit Architecture …………………………… 40
Chapter 4 NEW TECHNIQUE FOR BIST ………………………… 43
4-1 Introduction ……………………………………………… 43
4-2 Additional Bit Counter ………………………………… 45
4-3 The Proposed Embedding Algorithm …………………… 48
Chapter 5 SIMULATION RESULTS ……………………………… 52
5-1 Comparison with previous work …………………………53
Chapter 6 CONCLUSIONS …………………………………………54
References ……………………………………………………… 55
Figure 1.1 Architecture of the BIST ……………………… 1
Figure 1.2 Principle of testing …………………………… 4

Figure 2.1 A circuit of fault-free and faulty ………… 8
Figure 2.2 An example of single stuck-at fault model… 8
Figure 2.3 A three-input NAND gate with, (a) no faults (b) x1 with ans-a-0 fault, and (c) x1 with an s-a-1 fault…9
Figure 2.4 An example of a single stuck-at fault …… 11
Figure 2.5 A test for x1 s-a-0 detects a different between the faulty circuit and the fault-free circuit …………12
Figure 2.6 Calculated the fault coverage ……………… 13
Figure 2.7 An example of parallel fault simulation … 18
Figure 2.8 A 4-stage LFSR connected to a chain ……… 19
Figure 2.9 The remaining equations of the scan flip-flops ………………………………………………………………………20
Figure 2.10 The matrix which represents the equations 20
Figure 2.11 Exhaustive pattern generator ……………… 24
Figure 2.12 Backtracing for pseudo-exhaustive testing 25
Figure 2.13 Standard linear feedback shift register… 26
Figure 2.14 Test-Per-Clock scheme …………………………28
Figure 2.15 Test-Per-Scan scheme ………………………… 29
Figure 2.16 STUMPS test-per-scan testing system ………30
Figure 3.1 Example of a Rectangle in the B-Matrix and its Corresponding Bit-Fixing Logic …………………………… 33
Figure 3.2 Cube Mapping with Source Cube and Image cube ………………………………………………………………………34
Figure 3.3 Block Diagram for Generating Transformed patterns ………………………………………………………… 35
Figure 3.4 Output cones ………………………………………37
Figure 3.5 General and independent of the underlying BIST scheme …………………………………………………………… 38
Figure 3.6 4-stage LFSR with reseeding circuit ……… 39
Figure 3.7 The architecture of modifying-bit ………… 40
Figure 3.8 Obtaining the useful pattern …………………41
Figure 4.1 Block diagram for parallel generation of useful patterns ………………………………………………………… 44
Figure 4.2 The example of the method which uses an additional bit counter (4 bits) ……………………………46
Figure 4.3 The example of the method which uses an additional bit counter (10 bits) ………………………………………………………………………44
Figure 4.4 Example of seed computing …………………… 48
Figure 4.5 The system view of BIST environment ……… 51
Table 2.1 The system of test-per-clock is different from system of the test-per-scan …………………………………31
Table 5.1 SCAS 89 circuits used in the experiments … 52
Table 5.2 Comparison of our technique and [6] …………53
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