隨著穿戴式電子產品的蓬勃發展，IC產業也越來越專注在超低電壓、超低功耗、高整合度…等等方面設計，而數位式低壓降線性穩壓器不僅能操作在超低電壓，也因為不需使用外接電感元件故有體積小的優勢，所以較常被使用在可攜式產品中。此論文提出具雙調節機制之超低電壓數位式非同步低壓降線性穩壓器，論文使用TSMC 90nm 1P9M製程作設計，電路操作在輸入電壓0.35V，可以提供輸出負載電流240μA至2.4mA之0.3V電壓，而此電壓可以供給許多系統作使用例如:感測器、類比數位轉化器、靜態隨機存取記憶體…等等。
此研究採用數位式非同步控制迴路，相對於大家熟悉的同步電路先天上設計有些限制與缺點，非同步電路設計由於不需要用到整體時脈(Global Clock)，而有下列優點:低功率消耗、操作速度快、無時脈分配效應(Clock Distribution)、無時脈歪斜效應(Clock Skew)以及不受快速時脈振盪所造成的磁波干擾(Electro Magnetic Interference, EMI)。此外非同步系統的另一個優點為易於日後功能與效能的升級，因設計者只需將任一塊運算速度較慢的電路做更換即可提升整體效能；高容錯也是非同步系統的優點，當非同步系統其中有一塊電路運算耗費比預期更多時間時，唯一影響的就是整體系統會花較長的時間完成運算，而同樣的情形發生在同步系統中則可能造成全系統功能錯誤。此論文之另一重點為粗、細雙調節機制，在粗調節模式下將藉由尺寸較大的功率電晶體迅速的提供大量電流以有效的提升整體系統追鎖速率，降低暫態響應時間也能提升系統負載調節率，而在粗調節模式追索完成後系統將切換至細調節模式，透過小尺寸的功率電晶體達到降低輸出電壓漣波的目的此機制除了能提供更大範圍的負載電流外，也能夠在細調節模式時降低輸出電壓漣波，輸出更穩定的電壓。除此之外改良過的電路架構也大大降低需要兩組相同的非同步控制電路的缺點，大幅降低製造成本。
在未來的電源管理系統中需要輸出多組不同電壓供電，因此如何克服不同輸出間能夠不互相影響，並且抗製程、溫度、電壓變異…等，將是未來發展方向之一；隨著綠能觀念的意識抬頭，電源管理系統也更重視獵能電路的發展，因此如何設計一高效能的電源管理系統以用來結合獵能趨勢，也必然是電源管理系統最大的挑戰，以上為此論文未來研究發展的方向以及重點。

With the proliferation of wearable electronics products, IC industry will focus on Ultra-Low voltage, Ultra-Low power, high degree of integration. Digital Low-Dropout Regulator can operate in ultra-low voltage. Because not to need extra inductance, it has the advantage of small volume. It usually used in portable products. This paper proposed design of asynchronous digital low-dropout regulator with dual adjustment modes in ultra-low voltage input. The chip is fabricated by TSMC 90nm 1P9M process.The system operates in 0.35V input and 0.3V output. It can provide to lots of system, such as sensor, analog-to-digital convertor, SRAM, and so on. This research designed by digital asynchronous control loop. Compared with the familiar synchronous circuit, there are some limitations and shortcomings. The asynchronous circuit design has the following advantages, such as low power consumption, high operating system, no clock distribution, no clock skew and no electro magnetic interference. Another focus of this paper is the coarse and fine dual adjustment mechanism. In the coarse adjustment mode, a large amount of current can be quickly supplied by a large-sized power transistor to effectively improve the overall system tracking rate and reduce the transient response time. After the coarse adjustment mode is completed, the system will switch to the fine adjustment mode, and the output voltage ripple can be reduced by the small-sized power transistor. This mechanism can provide a larger range of load current. In addition, it is also possible to output a more stable voltage.
Keyword: Ultra-Low Power、Digital LDO、Asynchronous Control Loop、Dual Adjustment Modes、
High current efficiency

目錄
致謝	I
中文摘要	II
英文摘要	III
內文目錄	IV
圖目錄	VII
表目錄	XI
第一章  緒論	1
1.1 研究背景	1
1.2 研究動機	2
1.3 論文架構	3
第二章  低壓降線性穩壓器介紹	4
2.1 穩壓器的分類	4
2.1.1切換式電容穩壓器	5
2.1.2切換式穩壓器	7
2.1.3低壓降線性穩壓器	9
2.1.4 穩壓器比較	11
2.2低壓降線性穩壓器分類	12
2.2.1類比式低壓降穩壓器	12
2.2.2數位式同步低壓降線性穩壓器	13
2.2.3數位式非同步低壓降線性穩壓器	14
2.3 低壓降線性穩壓器之特性參數	15
2.3.1 輸出電壓差	16
2.3.2 靜態電流	17
2.3.3 線性調節率	17
2.3.4負載調節率	19
2.3.5 電源效率	20
2.3.6 輸出準確率	21

2.4 穩定性分析	23
2.4.1 暫態響應	26
2.4.2 頻率響應	29
第三章  文獻分析與探討	32
3.1 文獻分析	32
3.2 文獻比較	39
第四章  電路設計與模擬	40
4.1 超低電壓之具雙調節模式非同步數位式低壓降線性穩壓器設計	41
4.1.1 具時脈控制之比較器	42
4.1.2 Muller-C Element	43
4.1.3 切換式雙向非同步控制單元	44
4.1.4 有限狀態機	46
4.1.5 波峰偵測器	47
4.1.6 功率電晶體陣列	48
4.1.7 雙調節模式	49
4.2 電路佈局與模擬	51
4.2.1 全系統模擬結果	53
第五章  電路量測	63
第六章  結論與未來展望	64
參考文獻	65
 

圖目錄
圖1.1 系統單晶片	1
圖1.2同步數位式低壓降線性穩壓器	3
圖1.3同步數位式低壓降線性穩壓器特性	3
圖2.1升壓型切換式電容穩壓器	5
圖2.2切換式穩壓器基本架構	7
圖2.3低壓降線性穩壓器基本架構	9
圖2.4類比式低壓降線性穩壓器基本架構	12
圖2.5數位式同步低壓降線性穩壓器基本架構	14
圖2.6數位式非同步低壓降線性穩壓器基本架構	14
圖2.7低壓降線性穩壓器之輸入對輸出電壓曲線圖	16
圖2.8靜態電流示意圖	17
圖2.9低壓降線性穩壓器線性調節率示意圖	18
圖2.10低壓降線性穩壓器負載調節率示意圖	19
圖2.11輸出電壓誤差示意圖	21
圖2.12誤差放大器偏移圖	22
圖2.13電阻值誤差示意圖	22
圖2.14應用於SoC內的補償方式	25
圖2.15利用DFC調整相位邊限	25
圖2.16低壓降線性穩壓器與輸出電容及負載電流	26
圖2.17低壓降線性穩壓器輸出對負載電流反應圖	27
圖2.18低壓降線性穩壓器之交流分析等效模型	29
圖2.19等效串聯電阻過大與過小之影響	   31
圖3.1文獻[16]65奈米製程之數位控制低壓降線性穩壓器	33
圖3.2文獻[17]具雙調節機制與快速追索模式之LDO	34
圖3.3文獻[18]超低壓快鎖式數位控制低壓降線性穩壓器	35
圖3.4文獻[19]具雙控制迴路之低壓降線性穩壓器架構與操作流程	36
圖3.5文獻[20]雙向非同步低壓降線性穩壓器架構	37
圖3.6文獻[20]非同步控制單元架構	37
圖3.7文獻[21]自適性數位傳輸控制器	38
圖3.8文獻[21]列-欄-位元3-D功率級	.38
圖4.1全系統電路架構圖	40
圖4.2具時脈控制之比較器電路架構圖	42
圖4.3比較器電路遲滯曲線圖	42
圖4.4靜態Muller-C Element電路架構圖	43
圖4.5 Muller-C Element電路模擬圖	44
圖4.6切換式雙向非同步控制單元電路架構圖	45
圖4.7切換式雙向非同步控制單元電路模擬圖	45
圖4.8切換式雙向非同步控制單元電路模擬圖	45
圖4.9有限狀態機狀態圖	46
圖4.10有限狀態機電路架構圖	46
圖4.11有限狀態機模擬結果圖	47
圖4.12波峰檢測器電路架構圖	47
圖4.13波峰檢測器電路模擬圖	48
圖4.14功率電晶體陣列電路架構圖	49
圖4.15雙調節模式運作示意圖	50
圖4.16全系統架構圖	51
圖4.17電路佈局圖	52
圖4.18電路佈局位置示意圖	52
圖4.19 TT 0℃輕載→重載→輕載電路鎖定情形	53
圖4.20 TT 0℃重載→輕載→重載電路鎖定情形	53
圖4.21 TT 27℃輕載→重載→輕載電路鎖定情形	54
圖4.22 TT 27℃重載→輕載→重載電路鎖定情形	54
圖4.23 TT 75℃輕載→重載→輕載電路鎖定情形	54
圖4.24 TT 75℃重載→輕載→重載電路鎖定情形	55
圖4.25 SS 0℃輕載→重載→輕載電路鎖定情形	55
圖4.26 SS 0℃重載→輕載→重載電路鎖定情形	56
圖4.27 SS 27℃輕載→重載→輕載電路鎖定情形	56
圖4.28 SS 27℃重載→輕載→重載電路鎖定情形	56
圖4.29 SS 75℃輕載→重載→輕載電路鎖定情形	57
圖4.30 SS 75℃重載→輕載→重載電路鎖定情形	57
圖4.31 FF 0℃輕載→重載→輕載電路鎖定情形	58
圖4.32 FF 0℃重載→輕載→重載電路鎖定情形	58
圖4.33 FF 27℃輕載→重載→輕載電路鎖定情形	58
圖4.34 FF 27℃重載→輕載→重載電路鎖定情形	59
圖4.35 FF 75℃輕載→重載→輕載電路鎖定情形	59
圖4.36 FF 75℃重載→輕載→重載電路鎖定情形	59
圖4.37環境變異下輕載輸出電壓	60
圖4.38環境變異下重載輸出電壓	60
圖4.39環境變異下輕載最大暫態響應	61
圖4.40環境變異下重載最大暫態響應	61
圖5.1量測儀器與晶片腳位之量測環境連接圖	63



 
表目錄
表2.1 穩壓器之特性比較表	11
表2.2 NMOS與PMOS功率電晶體之比較表	23
表3.1 文獻比較表	39
表4.1 設計方法與重點	39
表4.2 Muller-C Element 真值表	43
表4.3 預計規格表與模擬結果	62
表4.4 本論文與參考文獻特性比較表	62

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