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系統識別號 U0002-1702201122385300
中文論文名稱 應用於動態多電壓調整之高效能低壓降線性穩壓器
英文論文名稱 High Performance Low Dropout Regulator for Dynamic Multi-Voltage Scaling Application
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 99
學期 1
出版年 100
研究生中文姓名 沈宗模
研究生英文姓名 Tsung-Mo Shen
學號 697450095
學位類別 碩士
語文別 中文
口試日期 2010-12-21
論文頁數 61頁
口試委員 指導教授-楊維斌
委員-江正雄
委員-陳科宏
委員-羅有龍
委員-施鴻源
中文關鍵字 低壓降線性穩壓器  動態電壓調整  快速響應 
英文關鍵字 LDO  DVS  Fast-transient response 
學科別分類 學科別應用科學電機及電子
中文摘要 本篇論文以應用於動態電壓調整(Dynamic Voltage Scaling)之低壓降線性穩壓器,根據控制回授電路來決定輸出電壓的大小,相較於以往回授電路控制DC-DC Converter的方式,這種方式能大幅縮短穩壓時間並減少功率消耗。在運算放大器方面,採用Gm-C電路來增加系統開迴路增益,但會降低系統的穩定性,因此在負載電晶體的閘極與汲極間加上米勒補償(Miller Compensation)來穩定系統的相位以確保輸出電壓穩定。
另外,為了大幅縮短多電壓切換時所需時間,提出一快速鎖定機制來針對低壓降線性穩壓器做快速穩壓,其設計重點在於,根據電流不同使得比較器的轉態點不同,這樣不僅能縮短穩壓時間也能減少晶片所需面積。因此,本篇論文以低壓降線性穩壓器根據回授電路的控制頻率或回授電阻的組合方式去降低/提高參考端的電壓準位以改變輸出電壓,並於電壓切換時透過快速鎖定機制去縮短穩壓時間並減少功率消耗,並針對運算放大器以及快速鎖定機制採用新架構設計,取代過去以回授電路控制DC-DC Converter的方式。
過去動態電壓調整常用於回授控制DC-DC Converter來調整輸出電壓降低功率消耗,但鎖定電壓時間過久造成不必要的功耗常為人所詬病。因此本篇論文針對此問題,採用回授控制低壓降線性穩壓器的方式取代DC-DC Converter,此回授路徑較短鎖定時間也較快,故能有效減少功率消耗。
英文摘要 Power management IC is used to control the multi-voltage of portable electrical applications to power up many functional blocks. A low dropout (LDO) regulator usually provides a regulated power source for noise-sensitive blocks behind a switching DC-DC converter. The LDO can save power dissipation effectively owing to which possessing two output voltage, high and low, used in dynamic voltage scaling (DVS), not only that the LDO is extensively used due to its accuracy output voltage, low-noise, and fast transient response. However, it trends low voltage, low quiescent current and low dropout of LDO design now. In other words, the stability and performance of the LDO needs to be trade-off.
The new dynamic fast settling low dropout regulator is presented for minimizing setting time in voltage switched by utilizing the Gm-C Operational Transconductance Amplifier (OTA) and fast-settling mechanism. The proposed LDO provides multiple discrete voltage levels of output by using multi-voltage control technique. Meanwhile, the settling time is reduced by utilizing dynamic fast-settling mechanism during output voltage switched. Furthermore, we propose the new comparator architecture to avoid the problems of overcharging and over-discharging at feedback node Vfb and output node Vout .The simulation results are based on 0.35μm CMOS process. The transient time of the proposed LDO is reduced from 4.2ms to 17μs. Moreover, the quiescent current of the Gm-C OTA circuit and fast-settling mechanism is 92μA in a heavy load condition.
論文目次 目錄
中文摘要 I
英文摘要 III
內文目錄 IV
圖表目錄 VII

第一章 緒論 1
1.1 研究背景與動機 1
1.2 設計流程與應用 2
1.3 論文架構 4

第二章 低壓降線性穩壓器 5
2.1低壓降線性穩壓器概論 5
2.2低壓降線性穩壓器之特性參數 6
2.2.1壓降電壓與靜態電流 7
2.2.2線性調節率與負载調節率 8
2.2.3電源效率與輸出準確率 11
2.3穩定性分析 12
2.3.1暫態響應 15
2.3.2頻率響應 17
2.4文獻回顧與探討 20
2.4.1具超級電流鏡之LDO架構 21
2.4.2快速變壓機制 22
2.4.3具動態偏壓校正機制之低壓降線性穩壓器 23
2.4.4可程式化輸出之低壓降線性穩壓器 23

第三章 可調式輸出電壓之低壓降線性穩壓器設計 25
3.1穩壓器設計 25
3.1.1誤差放大器 25
3.1.2快速穩壓機制 28
3.1.3輸出結構 30
3.2電路模擬與佈局 32
3.3量測考量與結果 42

第四章 應用於動態電壓調節系統之低壓降線性穩壓器 46
4.1 運算轉導放大器 46
4.2 快速穩壓機制架構 48
4.2.1轉態點可調式比較器 50
4.2.2相位頻率偵測器 51
4.2.3初始化機制 52
4.3 電路佈局與模擬 53

第五章 結論 58
5.1結論與未來展望 58

參考文獻 59

圖目錄

圖1.1晶片設計流程圖 3
圖2.1傳統低壓降線性穩壓器之電路圖 5
圖2.2低壓降線性穩壓器之輸出/入電壓曲線圖 7
圖2.3靜態電流示意圖 8
圖2.4低壓降線性穩壓器之線性調節率示意圖 9
圖2.5負載調節率示意圖 10
圖2.6輸出電壓誤差示意圖 11
圖2.7應用於SoC內的補償方式 14
圖2.8利用DFC電路調整相位邊限 14
圖2.9低壓降線性穩壓器與輸出電容 15
圖2.10輸出電壓對負載電流之反應圖 16
圖2.11低壓降線性穩壓器之交流分析等效模型 18
圖2.12等效串聯電阻過大或過小的情況 19
圖2.13輕、重載與ESR補償 20
圖2.14低電壓超級電流鏡電路 21
圖2.15快速變壓機制架構圖 22
圖2.16具偏壓調整之低壓降線性穩壓器 23
圖2.17可程式化輸出之低壓降線性穩壓器 24
圖3.1可調式輸出電壓之低壓降線性穩壓器 25
圖3.2單級運算放大器 26
圖3.3誤差放大器電路圖 28
圖3.4判斷電路與快速穩壓機制 29
圖3.5判斷電路之雙比較器 29
圖3.6以雙載子電晶體作為輸出結構 31
圖3.7可調式輸出電壓之低壓降線性穩壓器 32
圖3.8輕、重載時系統相位及增益 33
圖3.9電壓切換模擬圖(輕載) 34
圖3.10線性調節率模擬圖(重載) 35
圖3.11負載調節率模擬圖(輸出高壓2.8V) 35
圖3.12負載調節率模擬圖(輸出低壓1.3V) 36
圖3.13輸出電壓差模擬圖(error=5%) 37
圖3.14電路佈局圖 38
圖3.15電路佈局示意圖 38
圖3.16 post-layout simulation電壓切換模擬圖 39
圖3.17 post-layout simulation線性調節率模擬圖 39
圖3.18 post-layout simulation負載調節率模擬圖(高壓2.8V) 40
圖3.19 post-layout simulation負載調節率模擬圖(低壓1.3V) 40
圖3.20 post-layout simulation輸出電壓差模擬圖(error=5%) 41
圖3.21量測儀器示意圖 42
圖3.22 Bonding wire 之模型 42
圖3.23低壓量測圖(1.3V) 43
圖3.24高壓量測圖(2.8V) 44
圖3.25電壓切換量測圖(2.8V↔1.3V) 44
圖3.26上升時間量測圖 45
圖3.27下降時間量測圖 45
圖4.1傳統運算轉導放大器 46
圖4.2傳統OTA與新OTA之轉導 47
圖4.3新OTA電路圖 47
圖4.4 FSM概念圖 49
圖4.5 FSM概念波形圖 49
圖4.6 FSM整體電路圖 50
圖4.7可調式比較器電路圖 51
圖4.8轉態點可調概念圖 51
圖4.9 PFD電路與改良圖 52
圖4.10 PFD改良比較圖 52
圖4.11初始化機制說明 53
圖4.12電路架構圖 53
圖4.13輕、重載時系統相位及增益 54
圖4.14電壓切換模擬圖(輕載) 54
圖4.15線性調節率模擬圖(重載) 55
圖4.16負載調節率模擬圖(輸出高壓2.8V) 56
圖4.17負載調節率模擬圖(輸出低壓1.3V) 56
圖4.18輸出電壓差模擬圖(error=5%) 57

表目錄

表1.1線性穩壓器與切換式穩壓器之特性 2
表2.1文獻比較表 24
表3.1預計規格表 33
表3.2 pre-layout simulation results 37
表3.3 pre-sim.與post-sim.比較結果 41
表4.1 pre-layout simulation results 57
參考文獻 參考文獻

[1] Yat-Hei Lam and Wing-Hung Ki, “A 0.9V 0.35um Adaptively Biased CMOS LDO Regulator with Fast Transient Response,” IEEE International Solid-State Circuits Conference, pp. 442–626, Feb. 2008.
[2] Chunlei Shi, B. C. Walker, E. Zeisel, B. Hu and G. H. McAllister, “A Highly Integrated Power Management IC for Advanced Mobile Applications,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1723–1731, Aug. 2007.
[3] Sao-Hung Lu, Wei-Jen Huang and Shen-Iuan Liu, “A Fast-Recovery Low Dropout Linear Regulator for Any-Type Output Capacitors,” IEEE Asian Solid-State Circuits Conference, pp. 497–500, Nov. 2005.
[4] P.K.T. Mok, Ka Nang Leung, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation,” IEEE Journal of Solid-State Circuits, vol. 38, no.10, pp. 1691–1702, Oct. 2003.
[5] C. K.Chava and J. Silva-Martinez, “A Frequency Compensation Scheme for LDO Voltage Regulators,” IEEE Transactions on Circuits and Systems I, vol. 51, no.6, pp. 1041–1050, Jun. 2004.
[6] K. Onizuka and T. Sakurai, “VDD-Hopping Accelerator for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time,” IEEE Journal of Solid-State Circuits, vol. 41, no.4, pp. 2382–2389, Nov. 2006.
[7] Ying-Cheng Wu, Chun-Yueh Huang and Bin-Da Liu, “A low dropout voltage regulator with programmable output,” IEEE Conference on Industrial Electronics and Applications, pp. 3357–3361, May 2009.
[8] P.E. Allen and D.R. Holdberg, CMOS Analog Circuit Design. New York: Holt, Rinehart and Winston, 1987.
[9] Jeongjin Roh, “High-performance error amplifier for fast transient DC-DC converters,” IEEE Transactions on Circuits and Systems II, Exp. Briefs, vol. 52, no. 9, pp. 591–595, Sept. 2005.
[10] Hung-Chih Lin, Hsiang-Han Wu and Tsin-Yuan Chang, “An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement,” IEEE Transactions on Circuits and Systems II, Exp. Briefs, vol. 55, no. 9, pp. 853–857, Sept. 2008.
[11] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan and S. Borkar, “Area-Efficient Linear Regulator With Ultra-Fast Load Regulation,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 933–940, Apr. 2005.
[12] Hong-Wei Huang, Chia-Hsiang Lin and Ke-Horng Chen, “High-performance low-dropout regulator achieved by fast transient mechanism,” European Solid-State Circuits Conference, pp. 350–353, Sept. 2008.
[13] Zushu Yan, Liangguo Shen, Yuanfii Zhao and S. Yue, “A low-voltage CMOS low-dropout regulator with novel capacitor-multiplier frequency compensation,” IEEE International Symposium on Circuits and Systems, pp. 2685 – 2688, May 2008.
[14] 黃志揚, “低壓降線性穩壓器頻率補償之改善方法, ” NTHU碩士論文, Jun. 2004
[15] 張哲維,“具自我調變省電模式的低壓降線性穩壓器, ” NTHU碩士論文, Sept. 2007
[16] 黃柏勳,“利用負向主動回授技巧之低壓降穩壓器, ” NCTU碩士論文, Jan. 2006
[17] Chun-Yu Hsieh, Chih-Yu Yang and Ke-Horng Chen, “A Low-Dropout Regulator With Smooth Peak Current Control Topology for Over current Protection,” IEEE Transactions on Power Electronics, vol. 25, no. 6, pp. 1386-1394, Jun. 2010.
[18] Shangyang Xiao, Weihong Qiu, G. Miller, T.X. Wu, I. Batarseh, “An Active Compensator Scheme for Dynamic Voltage Scaling of Voltage Regulators, ” IEEE Transactions on Power Electronics, Vol. 24, no. 1, pp. 307-311, Jan. 2009
[19] Ka Nang Leung, Yuen Sum Ng, “A CMOS Low-Dropout Regulator With a Momentarily Current-Boosting Voltage Buffer,” IEEE Transactions on Circuits and Systems I, vol. 57, no. 9, pp. 2312-2319 sept. 2010
[20] M. El-Nozahi, A. Amer, J. Torres, K. Entesari, E. Sanchez-Sinencio, “High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique,” IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 565-577 Mar. 2010
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