低耗電高速低雜訊無線PLL 積體電路為近年來業界所發展的主要產品之一. 它的市場很大所以引起了各家廠商的投入., 所以它的規格要求可以說是要求很高. 不但要低耗電, 以維持長的電池使用時間及待機時間比其他廠商來得長; 也要求高速的下載速度及上載速度. 以提供更佳的文字或圖形傳送, 甚至是音樂資料或影片檔案的下載.
本文PFDCPSCPLL 可達4 Giga Hz, 1.47E-02 Watts, and 6.9E-19 SQ V/HZ使用了Phase Frequency Detector, Chare Pump Filter, Source Couple VCO 和 N Divider, 提供了完整低耗電高速低雜訊PFDCPSCPLL 設計的要點及大綱, 讓通訊積體電路或系統的設計者有一參考文獻.

The Low-Power High-Speed Low-Noise PLL is a significant circuit for portable consumer devices. There are many sorts of PLLs due to its huge market demand. Its main applications are portable phones and GPS devices. It requires low-power for allowing the battery has long-used time. Also it demands fast-download speed for text transmission or graphic transmission. Furthermore, it needs low-noise quality to assure excellent sound received quality.

	PFD_CP_SC_PLL can reach 4 Giga Hz, 1.47E-02 Watts, and 6.9E-19 SQ V/HZ composed by a Phase Frequency Detector, a Chare Pump Filter, a Source Couple VCO and a 64 Divider. This thesis offers a complete low-power, high-speed, and low-noise PFDCPSC PLL design concept and detailed circuits, allowing communication designers to have a great reference.

Table of Contents

Chinese Abstract………………………………………………………………II
English Abstract………                     ……………… III
List of Figures…………………………………………………… VII
List of Tables………………………………………………………IX
List of Appendix…………………………………………………  X

Chapter 1 General Theory of Phase Locked Loop………………………………………….1
1.1	Architecture of PLL ……………………………………………………………………3
1.2	The Phase Detector …………………………………………………………………….4
1.3	The Loop Filter …………………………………………………………………………9
1.4	The Voltage Controlled Oscillator …………………………………………………….12
1.5	What PFDCPSC PLL for ……………………………………………………………..15
1.6	Why PFDCPSC PLL ………………………………………………………………….16

Chapter 2 Design of Low Power High Speed Low Noise PFD_CP_SC_PLL …………..17
2.1 A system Noise Perspective ………………………………………………………......21
2.2 The PFD ………………………………………………………………………………23
2.3 The Charge Pump and the Loop Filter ……………………………………………….32
2.4 The Source Coupled Voltage Controlled Oscillator …………………………………37
2.5 64 Frequency Divider & Clock Synthesizer …………………………………………42

Chapter 3 Pspice Simulation ……………………………………………………..………45
3.1 High Speed Simulation  ……………………………………………………..………46
3.2 Low Power Simulation ………………………………………………………………..47
3.3 Low Noise Simulation ………………………………………………………………...48
3.4 The CIR(NET) Files …………………………………………………………………..51
3.5 Small Signal Bias Analysis …………………………………………………………...53
3.6 PLL Verilog Core Program …………………………………………………………...55
3.7 Transfer Function ……………………………………………………………………..56

Chapter 4 Conclusion …………………………………………………………………….57

Reference List……………………………………………………………………………..58
Appendix A: PLL Verilog core program…………………………………………………..60
Appendix B: Noise analysis by AC sweep at 4G Hz……….……………………………..75
Appendix C: The detail noise analysis of 150% VCO W…………..……………………..84
Appendix D: The CIR(NET) file..…………………………………..……………………..92
List of Figures
Figure 1. Block Diagram of PLL ………………………………………………………….3
Figure 2.The waveform of XOR PLL is below. ………….………………………………..5
Figure 3. The PFD schematic ………………………………………………………………7
Figure 4. PFD working waveform …………………………………………………………8
Figure 5. Tri-State Loop filter ……………………………………………………………...9
Figure 6.Charg pump loop filter …………………………………………………………..10
Figure7.Current Starved VCO …………………… ……………………………………...13
Figure 8. Source Coupled VCO schematic ……………………………………………….14
Figure 9. PFDCPSC PLL Model Schematic & Hierarchy Level Map ……………………17
Figure 10. MOSFET model parameters …………………………………………………..19
Figure 11. Brief noise analysis by AC sweep at 4G Hz…………………..……………….22
Figure 12. PFD schematic ………………………………………………………………...24
Figure 13. 2 port NAND gate……………………………………………………………..25
Figure 14. Three port NAND gate…………………………………………………………25
Figure 15. Four port NAND gate …………………………………………………………26
Figure 16. The CMOS Inverter …………………………………………………………...27
Figure 17 Lock time schematic from 2GHZ to 4GHZ…………………………………….28
Figure 18. Lock time for 2GHZ to 4GHZ ……………………………………………..….29
Figure 19.(A) Schematic of the PFD_PLL transferring from 3.3G HZ to 4G HZ ….……30
Figure 19.(B) Waveform of the PFD_PLL transferring from 3.3G HZ to 4G HZ…….…..31 
Figure 20(A). CP Loop filter symbolic  ……………………………………………..…..33
Figure 20(B)..Charge Pump Filter loop Schematic………………………………………33
Figure 21. CP filter current at 4G HZ ……………………………………………………35
Figure 22. CP_Filter input and output simulation at 4G HZ …….………………………36
Figure 23. Source Coupled VCO schematic ……………………………………………...37
Figure 24(A). The CP filter output voltage 4.859 V at 4 GHZ……..…………………….38
Figure 24(B). CP filter output voltage 4.858 V at 2 GHZ…………………………………39 
Figure 25. the M15 current, 230uA, is nearly double of M18 current,…………….……...40
Figure 26(A). Input and output voltage of VCO from 4GHZ to 4GHZ ………….….……40
Figure 26(B). Input and output voltage of VCO from 3GHZ to 4GHZ……….………….41
Figure 26(C). Input and output voltage of VCO from 2GHZ to  4GHZ…….…….…….41
Figure 27. D flip-flop ………………………………………………..…………………..42
Figure 28. 64 Frequency Divider & Clock Synthesizer ………………..………………...43
Figure 29. The PLL output signal at 4GHZ. From 3.5GHZ ………….….……………….46
Figure 30.The VCO’s schematic Wp*1.5, Wn*1.5 …………………………………….49
Figure 31. The brief noise analysis of 150% VCO W……………………………..………50
Figure 32. The PFD Nand4 CIR(NET) file …………………..………..…………………52
Figure 33. Verilog sample program by module …………..………………………………55
Figure 34. The phase transfer function performance …………………………………….56
List of Tables
Table 1. PFDCPSC PLL Specification …………………………………………………. 45
Table 2. PLL voltage source’s current and total power consumption ……………………47
Table 3. The noise result and comparison ………………………………………………..49
List of Appendix
Appendix A:PLL Verilog core program……..……………………………………………60
Appendix B: Noise analysis by AC sweep at 4G Hz……….……………………………..75
Appendix C: The detail noise analysis of 150% VCO W…………..……………………..84
Appendix D: The CIR(NET) file……….…………………………..……………………..92

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