系統識別號 | U0002-1508201917211300 |
---|---|
DOI | 10.6846/TKU.2019.00415 |
論文名稱(中文) | 超低電壓具多重相位觸發及自動變頻機制之數位式低壓降線性穩壓器 |
論文名稱(英文) | Digital Low-Dropout Regulator with Multiple Phase trigger and Automatic Frequency Conversion Mechanism in Ultra-Low Voltage Input |
第三語言論文名稱 | |
校院名稱 | 淡江大學 |
系所名稱(中文) | 電機工程學系碩士班 |
系所名稱(英文) | Department of Electrical and Computer Engineering |
外國學位學校名稱 | |
外國學位學院名稱 | |
外國學位研究所名稱 | |
學年度 | 107 |
學期 | 2 |
出版年 | 108 |
研究生(中文) | 介志中 |
研究生(英文) | Chih-Chung Chieh |
學號 | 605450104 |
學位類別 | 碩士 |
語言別 | 繁體中文 |
第二語言別 | |
口試日期 | 2019-06-28 |
論文頁數 | 72頁 |
口試委員 |
指導教授
-
楊維斌(robin@ee.tku.edu.tw)
委員 - 楊維斌(robin@ee.tku.edu.tw) 委員 - 江正雄(chiang@ee.tku.edu.tw) 委員 - 羅有龍(yllo@nknu.edu.tw) |
關鍵字(中) |
超低電壓 數位式低壓降線性穩壓器 同步控制迴路 多重相位觸發 自動變頻機制 |
關鍵字(英) |
Ultra-Low Voltage Digital LDO Synchronous Control Loop Mutiple phase trigger Automatic frequency conversion mechanism |
第三語言關鍵字 | |
學科別分類 | |
中文摘要 |
隨著穿戴式電子產品的蓬勃發展,IC產業也越來越專注在超低電壓、超低功耗、高整合度…等等方面設計,而數位式低壓降線性穩壓器不僅能操作在超低電壓,也因為不需使用外接電感元件故有體積小的優勢,所以較常被使用在可攜式產品中。此論文提出具雙調節機制之超低電壓數位式非同步低壓降線性穩壓器,論文使用TSMC 90nm 1P9M製程作設計,電路操作在輸入電壓0.5V,可以提供輸出負載電流600μA至2.4mA之0.3V電壓,而此電壓可以供給許多系統作使用例如:感測器、類比數位轉化器、靜態隨機存取記憶體…等等。 此研究採用數位同步式的設計,其電路複雜度相較於非同步式而言較為簡易,然而隨著通訊與手機產業的崛起,低壓降線性穩壓器除了不斷往快速響應的方向,系統中已逐漸以高轉換效率的理念並提高雜訊抑制能力來設計。在設計同步的時脈時頻率越高追鎖速度相對就會越快,但相對的電流效率會越來越低,因此如何在同一頻率的一個週期內做出更多的比較,就可以達到更快的鎖定速率、更高的電流轉換效率,即為本論文的研究出發點。 在未來的電源管理系統中需要輸出多組不同電壓供電,因此如何克服不同輸出間能夠不互相影響,並且抗製程、溫度、電壓變異…等,將是未來發展方向之一;隨著綠能觀念的意識抬頭,電源管理系統也更重視獵能電路的發展,因此如何設計一高效能的電源管理系統以用來結合獵能趨勢,也必然是電源管理系統最大的挑戰,以上為此論文未來研究發展的方向以及重點。 |
英文摘要 |
With the proliferation of wearable electronics products, IC industry will focus on Ultra-Low voltage, Ultra-Low power, high degree of integration. Digital Low-Dropout Regulator can operate in ultra-low voltage. Because not to need extra inductance, it has the advantage of small volume. It usually used in portable products. This paper proposed design of synchronous digital low-dropout regulator with multiple phase trigger and automatic frequency conversion mechanism in Ultra-Low Voltage Input. The chip is fabricated by TSMC 90nm 1P9M process. This system operates in 0.5V input and 0.3V output with the load current of 600μA to 2.4mA. It can provide to lots of system, such as sensor, analog-to-digital convertor, SRAM, and so on. This research designed by digital synchronous control loop. It’s circuit complexity is simpler than asynchronous control loop. When designing the synchronous architecture, high frequency can make tracking speed fast, but the max current efficiency will be lower. Therefore, how to make more comparisons in the same frequency is the most important idea in this project. When system is finished to track the correct output voltage and current, then Peak Detector will give a signal to DCO reduce the output frequency to half, used to reduce the power consumption. In the future power management system, it is necessary to output multiple sets of different voltages, so how to overcome the different outputs resistance to process, temperature, voltage variation, etc., , and the power management system pays more attention to the development of the hunting circuit. Therefore, how to design a high-performance power management system to combine the harvesting is also the biggest challenge of the power management system. |
第三語言摘要 | |
論文目次 |
目錄 致謝 I 中文摘要 II 英文摘要 III 內文目錄 IV 圖目錄 VII 表目錄 XI 第一章 緒論 1 1.1 研究背景與動機 1 1.2 論文架構 6 第二章 低壓降線性穩壓器介紹 7 2.1 穩壓器的分類 7 2.1.1切換式電容穩壓器 8 2.1.2切換式穩壓器 10 2.1.3低壓降線性穩壓器 12 2.1.4 穩壓器比較 14 2.2低壓降線性穩壓器分類 15 2.2.1類比式低壓降穩壓器 15 2.2.2數位式同步低壓降線性穩壓器 16 2.2.3數位式非同步低壓降線性穩壓器 17 2.3 低壓降線性穩壓器之特性參數 18 2.3.1 輸出電壓差 19 2.3.2 靜態電流 20 2.3.3 線性調節率 21 2.3.4負載調節率 22 2.3.5 電源效率 24 2.3.6 輸出準確率 24 2.4 穩定性分析 27 2.4.1 暫態響應 30 2.4.2 頻率響應 33 第三章 文獻分析與探討 37 3.1 文獻分析 37 3.2 文獻比較 43 第四章 電路設計與模擬 44 4.1 超低電壓之具雙調節模式非同步數位式低壓降線性穩壓器設計 45 4.1.1 具時脈控制之比較器 47 4.1.2 波峰偵測器 49 4.1.3 數位控制振盪器 52 4.1.4 移位暫存器 54 4.1.5功率電晶體陣列 55 4.2 電路佈局與模擬 56 4.2.1 全系統模擬結果 58 第五章 電路量測 68 5.1量測方式 68 第六章 結論與未來展望 69 參考文獻 70 圖目錄 圖1.1 (a)系統單晶片 2 (b)可攜式裝置之電源管理系統 2 (c)同步數位式低壓降線性穩壓器架構 5 (d)同步數位式低壓降線性穩壓器特性 5 圖2.1切換式穩壓器基本架構 8 圖2.2升壓型切換式電容穩壓器 10 圖2.3低壓降線性穩壓器基本架構 12 圖2.4類比式低壓降線性穩壓器基本架構 15 圖2.5數位式同步低壓降線性穩壓器基本架構 17 圖2.6數位式非同步低壓降線性穩壓器基本架構 18 圖2.7低壓降線性穩壓器之輸入對輸出電壓曲線圖 20 圖2.8靜態電流示意圖 21 圖2.9低壓降線性穩壓器線性調節率示意圖 22 圖2.10低壓降線性穩壓器負載調節率示意圖 23 圖2.11輸出電壓誤差示意圖 25 圖2.12誤差放大器偏移示意圖 26 圖2.13電阻值誤差示意圖 26 圖2.14應用於SoC內的補償方式 29 圖2.15利用DFC調整相位邊限 30 圖2.16低壓降線性穩壓器與輸出電容及負載電流 31 圖2.17低壓降線性穩壓器輸出對負載電流反應圖 31 圖2.18低壓降線性穩壓器之交流分析等效模型 33 圖2.19等效串聯電阻過大與過小之影響 35 圖3.1文獻[16]65奈米製程之數位控制低壓降線性穩壓器 38 圖3.2文獻[17]具雙調節機制與快速追索模式之LDO 39 圖3.3文獻[18]超低壓快鎖式數位控制低壓降線性穩壓器 40 圖3.4文獻[19]具雙控制迴路之低壓降線性穩壓器架構與操作流程 41 圖3.5 (a)文獻[29]雙緣觸發之同步架構 42 (b)文獻[29]單緣觸發之同步架構 42 圖4.1全系統電路架構圖 45 圖4.2 (a)同步式線性穩壓器電流效率與追鎖速度比較圖 46 (b)利用切相位在同頻率下加速追鎖速度示意圖 47 圖4.3具時脈控制之比較器電路架構圖 48 圖4.4比較器電路遲滯曲線圖 48 圖4.5波峰偵測器電路架構圖 49 圖4.6波峰偵測器電路模擬圖 50 圖4.7變頻機制操作示意圖 51 圖4.8系統操作模式示意圖 51 圖4.9數位控制振盪器電路架構圖 52 圖4.10延遲單元架構圖 53 圖4.11八相位時序模擬圖 53 圖4.12移位暫存器架構圖 54 圖4.13移位暫存器時序模擬圖 54 圖4.14功率電晶體陣列電路架構圖 55 圖4.15全系統架構圖 56 圖4.16電路佈局圖 57 圖4.17電路佈局位置示意圖 57 圖4.18 TT 0℃重載→輕載→重載電路鎖定情形 58 圖4.19 TT 27℃輕載→重載→輕載電路鎖定情形 59 圖4.20 TT 75℃輕載→重載→輕載電路鎖定情形 59 圖4.21 SS 0℃輕載→重載→輕載電路鎖定情形 60 圖4.22 SS 27℃輕載→重載→輕載電路鎖定情形 61 圖4.23 SS 75℃輕載→重載→輕載電路鎖定情形 61 圖4.24 FF 0℃重載→輕載→重載電路鎖定情形 62 圖4.25 FF 27℃輕載→重載→輕載電路鎖定情形 63 圖4.26 FF 75℃輕載→重載→輕載電路鎖定情形 63 圖4.27環境變異下輕載輸出電壓 64 圖4.28環境變異下重載輸出電壓 64 圖4.29環境變異下輕載最大暫態響應 65 圖4.30環境變異下重載最大暫態響應 65 圖5.1量測儀器與晶片腳位之量測環境連接圖 68 表目錄 表2.1 穩壓器之特性比較表 14 表2.2 NMOS與PMOS功率電晶體之比較表 27 表3.1 文獻比較表 43 表4.1 預計規格表與模擬結果 66 表4.2 本論文與參考文獻特性比較表 67 |
參考文獻 |
[1] H. Danneels, K. Coddens, and G. Gielen, “A Fully-Digital, 0.3V, 270 nW Capacitive Sensor Interface Without External References,” IEEE Proceedings of the ESSCIRC (ESSCIRC), pp. 287-290, Sep. 2011. [2] S. Y. Fan, M. K. Law, and P. I. Mak, “A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readout,” IEEE International Symposium on Integrated Circuits (ISIC), pp. 399-391, Dec. 2014. [3] A. Savaliya, and B. Mishra, “A 0.3V, 12nW, 47fJ/conv, Fully Digital Capacitive Sensor Interface in 0.18μm CMOS,” IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), pp. 1-6, Jan, 2015. [4] W. B. Yang, S. J. Xie and I. T. Chuo, “A 0.3V 1kb Sub-Threshold SRAM for Ultra-Low-Power Application in 90nm CMOS,” The 27th International Technical Conference on Circuit/Systems, Computers and Communications (ITC-CSCC), 15-18, Jul, 2012. [5] W. B. Yang, C. H. Wang, I. T. Chuo and H. H. Hsu, “A 300mV 10MHz 4kb 10T Subthreshold SRAM for Ultralow- Power Application,” IEEE International Symposium on Intelligent Signal Processing and Communication Systems, pp. 604-608, Nov, 2012. [6] L. Y. Chiou, C. R. Huang, C. C. Cheng, and Y. L. Tsai, “A 300mV Sub-1pJ Differential 6T Sub-threshold SRAM with Low Energy and Variability Resilient Local Assist Circuit,” IEEE International Symposium on Next-Generation Electronics (ISNE), pp. 337-340, Feb, 2013. [7] L. Liu, K. Ishikawa, and T. Kuroda, “A 720μW 873MHz-1.008GHz Injection-Locked Frequency Multiplier with 0.3V Supply Voltage in 90nm CMOS,” IEEE Symposium on VLSI Circuits (VLSIC), pp. C140-C141, Jun, 2013. [8] M. Mendizabel, and C. Chen, “A Low Power Demodulator Using Subthreshold Design,” IEEE Asia-Pacific Conference on Antennas and Propagation (APCAP), pp. 1190-1193, Jul, 2014. [9] C. E. Hsieh, and S. I. Liu, “A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 325-328, Nov, 2014. [10] W. Zhao, A. B. Alvarez, and Y. Ha, “A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter with Wide Conversion Range,” IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-5, Feb, 2015. [11] C. K. Chava and J. S. Martinez, “A Frequency Compensation Scheme for LDO Voltage Regulators,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 6, pp. 1041-1050, Jun. 2004. [12] 曾南雄, “無外部電容的CMOS低壓差線性穩壓器, ”國立交通大學電機學院IC設計產業研發碩士班碩士論文, Jan. 2007. [13] S. Lu, W. Huang and S. Liu, “A Fast-Recovery Low Dropout Linear Regulator for Any-Type Output Capacitors,” 2005 IEEE Asian Solid-State Circuits Conference, Hsinchu, pp. 497-500, 2005. [14] Ka Nang Leung and P. K. T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation,” in IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, Oct. 2003. [15] C. K. Chava and J. Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 6, pp. 1041-1050, June 2004. [16] Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P. Chen, K. Watanabe, M. Takamiya and T. Sakurai, “0.5-V Input Digital Low-Dropout Regulator LDO with 98.7% Current Efficiency and 2.7-μA Quiescent Current in 65 nm CMOS,” IEICE Transactions, vol. E94-C, no. 6, pp. 938-944, Jun. 2011. [17] Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “A Fully Integrated Digital LDO with Coarse-Fine-Tuning and Burst-Mode Operation,” IEEE Transactions on Circuits and Systems II, pp, 683-687, July. 2016. [18] W. B. Yang, Y. Y. Lin, Y. L. Lo , “Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input ,” Circuits, Systems, and Signal Processing(CSSP), vol. 36, pp 5041-5061, Dec. 2017 [19] J. Liu and Nima Maghari, “A Fully-Synthesizable 0.6V Digital LDO with Dual-Loop Control using Digital Standard Cells,” 2016 14th IEEE international New Circuits and Systems Conference (NEWCAS), Oct. 2016. [20] Y. H. Lee, S. Y. Peng, C. C. Chiu, A. C. H. Wu, K. H. Chen, Y. H. Lin, S. W. Wang, T. Y. Tsai, C. C. Huang and C. C. Lee, “A Low Quiescent Current Asynchronous Digital-LDO with PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement,” IEEE Journal of Solid-State Circuits, vol. 48, pp. 1018-1030, Apr. 2013. [21] Fan Yang and Philip K. T. Mok, “A Nanosecond-Transient Fine-Grained Digital LDO with Multi-Step Switching Scheme and Asynchronous Adaptive Pipeline Control,” IEEE Journal of Solid-State Circuits, vol. 52, pp.1-12, Jun. 2017. [22] I. E. Sutherland,“Micropipelines”, Communications of the ACM, vol. 32, no. 6, pp. 720–738, 1989. [23] C. H. van Berkel,“Beware the isochronic fork”, Report UR 003/91, Philips Research Laboratories, 1991. [24] V. B. Marakhovsky,“ Logic design of asynchronous circuits”, Slides on the course. CS&SE Department, SPbPU. [25] W. Yang, Y. Lin and Y. Lo, “Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in 90nm CMOS process,” 2014 International Conference on Information Science, Electronics and Electrical Engineering, Sapporo, pp. 1653-1656, 2014. [26] Y. Huang, Y. Lu, F. Maloberti and R. P. Martins, “A Dual-Loop Digital LDO Regulator with Asynchronous-Flash Binary Coarse Tuning,”2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018. [27] K. Woo, T. Kim, S. Hwang, M. Kim and B. Yang, “A fast-transient digital LDO using a double edge-triggered comparator with a completion signal,” 2018 International Conference on Electronics, Information, and Communication (ICEIC), Honolulu, HI, pp. 1-4, 2018. [28] Y. L. Lo and W. Jen, “A 0.7V Input Output-Capacitor-Free Digitally Controlled Low-Dropout Regulator with High Current Efficiency in 0.35um CMOS Technology,” Microelectronics Journal (MEJ), pp, 756-765, Aug. 2012. [29] Ki-Chan Woo, Tae-Woo Kim, Seon-Kwang Hwang, Mi-Jeong Kim, and Byung-Do Yang, “A Fast-Transient Digital LDO Using A Double Edge-Triggered Comparator With A Completion Signal,” 2018 International Conference on Electronics, Information, and Communication (ICEIC) ,2018. |
論文全文使用權限 |
如有問題,歡迎洽詢!
圖書館數位資訊組 (02)2621-5656 轉 2487 或 來信