在現今的片上系統（SOC）設計中，由於現代積體電路(IC)複雜性的迅速增長，伴隨而來的是大量的測試資料以及測試時間的增加，由於測試通道容量的不足以及自動測試設備（ Automatic Test Equipment, ATE）的記憶體限制。因此掃描測試數據壓縮顯得特別重要。
    本文展示了單輸入通道多掃描鏈擴展比如何有助於在片上系統中獲得高測試數據壓縮，單輸入通道利用一連串的D-flip flop(DFF)將測試資料擴展到各個掃描鏈，這可以減少面積開銷以及能有效且大量的減少測試資料的使用，而多重掃描鏈擴展比能提高整體測試壓縮比以及縮短測試應用時間，首先掃描鏈在高擴展比底下呈現數量較多且長度較短的狀態，接著透過掃描鏈相互連接來降低擴展比以測得在高擴展比底下不能偵測到的錯誤。並且在連接過程中考慮掃描鏈的長度，以減少測試應用時間。

In today's system-on-a-chip (SOC) design, due to the rapid growth of the complexity of modern integrated circuits (ICs), a large amount of test data and test time increase, due to insufficient test channel capacity and automatic test equipment (Automatic Test Equipment, ATE) memory limitations. Therefore, scanning test data compression is particularly important.
     This article shows how single-input channel multi-scan chain scaling ratios can help achieve high test data compression in a system-on-a-chip. Single-input channels use a series of D-flip flops (DFF) to extend test data to individual scan chains, which reduces The area overhead and the effective and substantial reduction of the use of test data, and the multiple scan chain expansion ratio can improve the overall test compression ratio and shorten the test application time. First, the scan chain is presented in a large number and a short length under a high expansion ratio. Then, the scan chains are connected to each other to reduce the expansion ratio to detect errors that cannot be detected at a high expansion ratio. And consider the length of the scan chain during the connection process to reduce test application time.

目錄
致謝	I
中文摘要	II
英文摘要	III
目錄	IV
圖目錄	VI
表目錄	VII
第一章 緒論	1
1.1 研究背景	1
1.2 研究動機與目的	2
1.3 論文架構	3
第二章 背景知識與相關研究	4
2.1 故障模型	4
2.1.1 固定型故障	5
2.1.2 轉態延遲故障	5
2.2 固定型故障檢測	6
2.3 測試模擬	10
2.4 掃描單元設計	13
2.5 掃描鏈設計	14
第三章 先前準備	15
3.1 單測試輸入通道	16
3.2 掃描鏈多重擴展比	17
第四章 論文方法	19
4.1 掃描單元分組	19
4.1.1 廣度優先搜尋法(Breadth-First Search)	22
4.2 單測試輸入通道應用	24
4.3 掃描鏈多重擴展比應用	26
4.4 單測試輸入通道多重擴展比架構	28
第五章 實驗結果	30
第六章 結論與未來展望	32
參考文獻	33
 
圖目錄
圖 2.1 投值後抓值測試示意圖	5
圖 2.2 AND gate故障檢測的示例	6
圖 2.3 OR gate故障檢測的示例	7
圖 2.4 電路中可能包含的錯誤	8
圖 2.5 故障傳遞	12
圖 2.6 scan DFF	13
圖 2.7 scan chain	14
圖 3.1 單測試輸入通道架構	17
圖 3.2掃描鏈多重擴展比架構	18
圖 4.1掃描壓縮結構中的三種故障覆蓋損失	21
圖 4.2 BFS演算法	23
圖 4.3單測試輸入通道應用	25
圖 4.4掃描鏈多重擴展比應用	26
圖 4.5單測試輸入通道多重擴展比架構	29

 
表目錄
表 2.1故障覆蓋率	9
表 2.2邏輯閘錯誤傳遞情形	11
表 5.1電路資訊	30
表 5.2實驗結果	31

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