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系統識別號 U0002-1506200616580200
中文論文名稱 應用於H.264/AVC之低記憶體成本去方塊濾波器硬體架構
英文論文名稱 Efficient VLSI architecture with Low-memory cost for Deblocking Filter used in H.264/AVC
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 94
學期 2
出版年 95
研究生中文姓名 陳延任
研究生英文姓名 Yen-Jen Chen
學號 693390063
學位類別 碩士
語文別 中文
口試日期 2006-06-09
論文頁數 47頁
口試委員 指導教授-江正雄
委員-陳德勝
委員-江正雄
委員-蔡宗漢
委員-游 竹
委員-董蘭榮
中文關鍵字 H.264  去方塊濾波器  去方塊  濾波器 
英文關鍵字 H.264  Deblocking  filter 
學科別分類 學科別應用科學電機及電子
中文摘要 在資訊科技蓬勃發展的今日,各類多媒體應用普遍結合網際網路,例如:視訊會議、隨選視訊、影像監控,等等。雖然今日的網路技術已經到達寬頻,但是在使用人數的增加以及對畫面品質的要求下,網路頻寬勢必很快便會達到飽和,所以需要數位影音壓縮技術將大量多媒體資料作壓縮,使得在現有的儲存空間下,能夠容納更多的多媒體資料,進一步減少在網際網路上傳送資料的時間。
現代多媒體影像壓縮系統中如MPEG-1、MPEG-2、MPEG-4、H.261、H.263以及H.264,離散餘旋轉換(BDCT)是被廣為採用的影像壓縮方法,但是此方法有著一個缺點,就是在壓縮過程的取樣化(Quantization)下,在反離散餘旋轉換(IDCT)時,相鄰的兩個畫面方塊無法完美的接合在一起,因此觀賞者可以輕易的注意到畫面上的方塊,使得畫面的品質下降,此現象會隨著取樣係數的提高而更加顯著。
在目前最新的影像壓縮系統H.264中,去方塊效應濾波器(Deblocking filter)被整合融入成為系統的一部分(In-loop filter),相較於傳統的去方塊效應濾波器僅在解碼端之後(Post-filtering)的畫面作過濾的動作,內建的去方塊效應濾波器讓過濾後的畫面成為參考影像,且H.264制定的去方塊效應濾波器本身提供了一致性,可高度調適不同畫面來源,並獲得不錯的效果。
在影像解碼階段,去方塊濾波器需要相當大的運算量,若是完全使用軟體來計算,將會佔用大量的系統頻寬,所以需要硬體去方塊濾波器,本論文提出一個有效的去方塊濾波器的硬體設計,可以減少去方塊濾波器運算時間,同時降低系統匯流排的使用。相較於之前學者所提出的硬體架構,本論文藉由Dual-port SRAM及Two-port SRAM架構,使用鋸齒的方式來儲存資料,省下轉置矩陣的使用,使得電路面積變小,同時使用平行處理單元,使處理速度提高。
英文摘要 In video coding systems such as MPEG-1, MPEG-2, MPEG-4, H.261, H.263 and H.264, the Block-based Discrete Cosine Transform (BDCT) is widely used. The drawback of BDCT is the coarse quantization of the transform coefficients that can cause visually disturbing discontinuities.
In H.264/MPEG-4 AVC video coding standard, the deblocking filter has been integrated into the video CODEC. The filtered frames are used as reference frames for motion compensation. Compared with the post-deblocking-filter, the in-loop deblocking filter provides a certain level of quality, without an extra frame buffer, and can improve both objective and subjective qualities of the video stream.
The deblocking filtering process needs complex operation, and it may take of the decoding time. In order to increase the efficiency a hardwareized deblocking filter is necessary. We proposed an efficient deblocking filter in the thesis. Compared with the previous deblocking filters, the proposed architecture based on skewed memory adopts a 2-dementional parallel memory access without transforming the register memory. The new scheme can increase the throughput of deblocking filtering, and reduce the hardware cost.
論文目次 目錄

誌謝....................................................................................................................I
中文摘要..........................................................................................................II
英文摘要.........................................................................................................IV
目錄..................................................................................................................V
圖目錄..........................................................................................................VII
表目錄.............................................................................................................IX
第一章 緒論.....................................................................................................1
1.1 簡介.....................................................................................................1
1.2 研究動機.............................................................................................2
1.3 論文架構.............................................................................................4
第二章 去方塊濾波器演算法.........................................................................5
2.1 H.264/AVC系統介紹...........................................................................5
2.1.1 H.264/AVC系統架構簡介.........................................................6
2.1.2 畫面內預測...............................................................................7
2.1.3 移動補償預測.........................................................................10
2.1.4 轉換、量化與熵編碼器..........................................................11
2.2 H.264/AVC去方塊濾波器.................................................................12
2.2.1 過濾順序.................................................................................14
2.2.2 邊界強度.................................................................................17
2.2.2.1 閥值 與 定義...................................................................19
2.2.2.2 當邊界強度為1到3時的過濾模式....................................21
2.2.2.3 當邊界強度為4時的過濾模式...........................................22
2.3 目前已提出有效的去方塊濾波器系統架構...................................23
第三章 硬體架構設計..................................................................................25
3.1 資料處理流程...................................................................................27
3.2 內部記憶體規劃..............................................................................29
3.3 管線式去方塊濾波器模組..............................................................33
3.3.1旗標運算單元..........................................................................34
3.3.2邊界強度為1到3.....................................................................35
3.3.3邊界強度為4............................................................................36
3.3.4管線式濾波器運算分解...........................................................37
第四章 模擬結果與比較..............................................................................40
第五章 結論...................................................................................................44
參考文獻........................................................................................................45
圖目錄

圖 2.1 H.264/AVC壓縮端架構圖...........................................................6
圖 2.2 H.264/AVC解碼端架構圖...........................................................7
圖 2.3 INTRA_4x4 亮度預測方向........................................................8
圖 2.4 INTRA_4x4 亮度預測模式........................................................9
圖 2.5 INTRA_16x16 亮度預測模式....................................................9
圖 2.6 移動補償巨方塊四種模式.........................................................11
圖 2.7 移動補償8x8方塊四種模式......................................................11
圖 2.8 符合過濾條件的區塊邊界.......................................................14
圖 2.9 光柵掃描....................................................................................15
圖 2.10 掃描順序....................................................................................16
圖 2.11 垂直邊界與水平邊界之過濾....................................................17
圖 2.12 邊界強度決策樹........................................................................18
圖 2.13 巨方塊邊界強度的對應位置....................................................19
圖 3.1 提出的去方塊濾波器系統架構圖...........................................26
圖 3.2 資料處理順序............................................................................28
圖 3.3 去方塊濾波器時序規劃.........................................................29
圖 3.4 記憶體存取示意圖....................................................................31
圖 3.5 記憶體模組示意圖....................................................................32
圖 3.6 管線式去方塊濾波器模組架構圖............................................34


表目錄

表 3.1 邊界強度為1、2、3的輸出選擇表.............................................36
表 3.2 邊界強度為4的輸出選擇表....................................................37
表 4.1 硬體電路設計比較表...............................................................43

參考文獻 [01] Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T) Reference H.264/ISO/IEC 14496-10 AVC, Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEC, JVTG050, 2003.
[02] P. List, A. Joch, J. Lainema, G. Bjøntegaard, and M. Karczewicz, “Adaptive deblocking filter,” IEEE Transactions on Circuits and System for Video Technology, vol. 13, pp. 614–619, July 2003.
[03] T. Wiegand, G. J. Sullivan, G. Bjøntegaard, and A. Luthra, “Overview of the H.264/AVC video coding standard,” IEEE Transactions on Circuits and System for Video Technology, vol. 13, pp. 560–576, July 2003.
[04] Iain E. G. Richardson, H.264 and MPEG-4 Video Compression- Video Coding for Next-generation Multimedia, John Wiley & Sons Ltd., 2003.
[05] MPEG video group, MPEG-4 Video Verification Model Version 8.0, ISO/IEC JTC1/SC29/WG11 N1796, July 1997.
[06] A.Luthra, G.. J. Sullivan, and T. Wiegand, “Introduction to the Special Issue on the H.264/AVC Video Coding Standard,” IEEE Transactions on Circuits and Systems for Video Technology, 2003.
[07] J. Ostermann, J.Bormans, P.List, D.Marpe, M. Narroschke, F. Pereira, T. Stockhammer, and T. Wedi, “Video coding with H.264/AVC: Tools, performance, and complexity,” IEEE Magazine Circuits and Systems, First quarter 2004.
[08] K. Denolf, C. Blanch, G. Lafruit, and J. Bormans, “Initial memory complexity analysis of the AVC codec,” IEEE Workshop on Signal Processing Systems, pp.222–227, Oct. 2002.
[09] M. Horowitz, A. Joch, F. Kossentini, and A. Hallapuro, “H.264/AVC baseline profile decoder complexity analysis,” IEEE Transactions on Circuits and System on Video Technology, vol.13, no.7, pp.704–716, July 2003.
[10] Y.-W. Huang, T.-W. Chen, B.-Y. Hsieh, T.-C. Wang, T.-H. Chang, and L.-G. Chen, “Architecture design for deblocking filter in H.264/JVT/AVC,” Proceedings of IEEE International Conference on Multimedia and Expo, vol.1, pp.693–696, July 2003.
[11] M. Sima, Y. Zhou, and W. Zhang, “An efficient architecture for adaptive deblocking filter of H.264/AVC video coding,” IEEE Transactions on Consumer Electronics, vol. 50, pp. 292-296, 2004.
[12] L. Li, S. Goto, and T. Ikenaga, “A Highly Parallel Architecture for Deblocking Filter in H.264/AVC,” IEICE Transactions on Information and Systems, vol. E88-D NO.7, pp.1623-1629, July 2005.
[13] V. Venkatraman, S. Krishnan, and N. Ling, “Architecture for deblocking filter in H.264,” Picture Coding Symposium, 2004.
[14] C.-C. Cheng, and T.-S. Chang, “An hardware efficient deblocking filter for H.264/AVC,” IEEE International Conference on Consumer Electronics, pp. 235–236, 2005.
[15] S.-C. Chang, W.-H. Peng, S.-H. Wang, and T. Chiang, “A platform based bus-interleaved architecture for deblocking filter in H.264/MPEG-4 AVC,” IEEE Transactions on Consumer Electronics, vol. 51, pp. 249-255, 2005.
[16] B. Sheng, W. Gao, and D. Wu, “An implemented architecture of deblocking filter for H.264/AVC,” IEEE International Conference on Image Processing, vol. 1, pp. 665–668, 2004.
[17] G. Zheng, and L. Yu, “An efficient architecture design for deblocking loop filter,” Picture Coding Symposium, 2004.
[18] T.-M. Liu, W.-P. Lee, T.-A. Lin, and C.-Y. Lee, “A memory-efficient deblocking filter for H.264/AVC video coding,” IEEE International Symposium on Circuit and Systems, 2005.
[19] S.-Y. Shih, C.-R. Chang, and Y.-L. Lin, “A near optimal deblocking filter for H.264 Advanced Video Coding,” Asia South Pacific Design Automation Conference, pp. 24-27, 2006.
[20] JVT H.264/AVC Reference Software JM 9.5.
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