隨著超大型積體電路(VLSI ,Very large scale integration)的演進逐漸演變成系統單晶片(SOC ,System-on-a-chip)設計，一顆系統晶片包含很多可以重複使用的矽智財(IP ,Intellectual property)。現今都希望從IC設計開始到市場販售的時間越短越好，設計發展至今，IC設計變的越來越複雜，體積也越來越小，IC的測試已不像從前那麼簡單了，原本IC設計工程師只需要專注於IC的設計，解決設計上的問題，但當結合不同功能的模組後，在系統上可能會產生測試問題，例如某些情況下策是不可行又或者測試成本過高，導致IC設計工程師不再只注重IC設計的問題，必須再去考慮可測試性，降低測試的成本，這種步驟稱之可測試設計。測試的元件不能增加晶片的功能性還會增加成本，但可以確保此塊晶片的品質。
	每個待測電路的測試樣本(Test Pattern)分成測試的輸入和輸出兩部分，輸入和輸出是由自動化測試儀器(ATE , Auto Test Equipment)負責控制，ATE是主要的測試成本，為了使自動化測試儀器降低成本嵌入了解壓縮器和壓縮器，因此可以減少匯流排的頻寬和減少記憶體的儲存空間。
	IC測試發展至今所需要的測試樣本在測試輸出結果皆有未知值(X)混在其中，導致壓縮器的輸出信號失去可靠性，那要提高可靠性勢必得要有一套將未知值過濾掉的方法，也勢必得去增加控制資料去過濾未知值。
	而本篇文章提出的方法，也是必須先經過錯誤模擬(Fault Simulation)去產生測試樣本，即可知道該電路輸入甚麼測試樣本正常情況會出現甚麼樣的結果，即可預先知道未知值會出現在哪個位置，再透過後端的AND閘去過濾未知值，則AND閘一端接在電路的輸出，另一端則須要控制的資料，則我們將會去壓縮這些控制資料，儲存於ATE裡，則測試的過程則是上半部還是輸入測試樣本，下半部則輸入壓縮過後的控制資料，在利用計數器(Counter)的配合去還原成原來的控制資料傳給AND閘，這樣即可過濾未知值。
	該方法經過測試的結果未知值所佔比例越少，則控制資料壓縮的效果就會越好，再根據未知值分布的情況，利用不同壓縮方式選擇最好的去當我們的控制資料，這樣額外增加的控制資料成本就會比較低，這種方式將比一對一去檔未知值的方式好上很多，同時也可以維持原來的錯誤覆蓋率。

With the recent development of IC testing, IC designs have become more complex and smaller in size. Testing IC is no longer an easy task comparing to before, which inevitably reflects on the increase of testing costs. 
Unknown value(X) has always been presented in testing patterns data, therefore losing the accountability of the compressor’s output signal. In order to overcome this problem, the amount of controlled data needs to be increasing and there needs to be a better way to filter out the unknown value. 
This study will demonstrate various methods of IC testing when having different distribution of unknown value, achieving the goal of filtering out the unknown value, lowering the amount of required data and maintaining the initial fault coverage all at the same time.

目錄
中文摘要	I
英文摘要	III
目錄	IV
圖目錄	V
表目錄	VI
Chapter 1	緒論	1
1-1	研究背景與動機	1
1-2	論文簡介	3
1-3	論文總覽	5
Chapter 2	論文內運用的知識	6
2-1	Fault要如何偵測	6
2-2	Fault Coverage	7
2-3	Fault模擬	9
2-4	壓縮量計算	11
2-5	X-遮罩[21]	12
Chapter 3	硬體架構	14
3-1	硬體架構總覽	14
3-2	硬體結構細節說明	15
Chapter 4	實驗結果	23
4-1	實驗結果說明	23
Chapter 5	結論	28

圖目錄
圖 1.1 EDT架構	1
圖 2.1 AND-fault detect	6
圖 2.2 XOR-fault detect	7
圖 2.3 Fault Coverage	8
圖 2.4平行錯誤模擬	9
圖 2.5 X-遮罩邏輯	12
圖 3.1 硬體架構	14
圖 3.2 輸出資料與控制資料位置關係	15
圖 3.3 流程圖	18
圖 3.4 細部架構 (採用壓縮後控制資料)	19
圖 3.5 細部架構 (非採用壓縮後控制資料)	21
圖 4.1 實驗結果綜合比較	23

表目錄
表 2 1 X-遮罩輸入輸出的關係	13
表 4.1 採用5%實驗結果	24
表 4.2 採用10%實驗結果	25
表 4.3  採用15%實驗結果	26
表 4.4  採用20%實驗結果	27

[1]	W. Rajski and J. Rajski, “Modular compactor of test responses,” Proc. VTS, pp. 242-251, 2006.
[2]	S. Mitra and K. S. Kim, “X-Compact: an efficient response compaction technique,” IEEE Trans. CAD, vol. 23, pp. 421- 432, March 2004.
[3]	J. H. Patel, S. S. Lumetta, and S. M. Reddy, “Application of Saluja-Karpovsky compactors to test responses with many unknowns,” Proc. VTS, pp. 107-112, 2003.
[4]	T. Clouqueur, H. Fujiwara, K. Zarrineh, and K. Saluja, “Design and analysis of multiple-weight linear compactors of responses containing unknown values,” Proc. ITC, pp. 1099-1108, 2005.
[5]	J. Rajski, J. Tyszer, C. Wang, and S. Reddy, “Convolutional compaction of test responses,” Proc. ITC, pp.745-754, 2003.
[6]	C. Wang, et al., “On compacting test responses data containing unknown values,” Proc. ICCAD, pp. 855-862, 2003.
[7]	C. Barnhart, et al., “OPMISR: The foundation for compressed ATPG vectors,” Proc. ITC, pp. 748-757, 2001.
[8]	J. Rajski, et al., “Embedded deterministic test for low cost manufacturing test,” Proc. ITC, pp. 301-310, 2002.
[9]	H. Tang, et al., “On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios”, Proc. VLSI Design, pp. 59-64, 2005. 
[10]	M. Naruse, I. Pomeranz, S.M. Reddy, and S. Kundu, “On chip compression of output responses with unknown values using LFSR reseeding,” Proc. ITC, pp. 1060-1068, 2003.
[11]	S. Wang, K.J. Balakrishnan, and W. Wei, “X-Block: An efficient LFSR reseeding-based method to block unknowns for temporal compactors,” IEEE Trans. Comput, vol. 57, pp. 978-989, July 2008.
[12]	S. Wang, W. Wei, and S.T. Chakradhar, “Unknown blocking scheme for low control data volume and high observability,” Proc. DATE, pp. 1 – 6, 2007.
[13]	E.H. Volkerink and S. Mitra, “Response compaction with any number of unknowns using a new LFSR architecture,” Proc.DAC, pp. 117-122, 2005.
[14]	P. Wohl, J.A. Waicukauski, S. Patel, and A. Amin, “X-tolerant compression and application of scan-ATPG patterns in a BIST architecture,” Proc. ITC, pp. 727-736, 2003.
[15]	Y. Tang, et al., “X-masking during logic BIST and its impact on defect coverage,” Proc. ITC, pp. 442-451, 2003.
[16]	I. Pomeranz, S. Kundu, and S. M. Reddy, “On output response compression in the presence of unknown output values,”Proc. DAC, pp. 255-258, 2002.
[17]	V. Chickermane, B. Foutz, and B. Keller, “Channel masking synthesis for efficient on-chip test compression,” Proc. ITC,pp. 452-461, 2004.
[18]	S. Mitra, S.S. Lumetta, M. Mitzenmacher, “X-tolerant signature analysis,” Proc. ITC, pp. 432-441, 2004.
[19]	O. Sinanoglu and S. Almukhaizim, “X-Align: Improving the Scan Cell Observability of Response Compactors,” Very Large Scale Integration (VLSI) Systems, IEEE Trans, vol. 17, Oct 2009, pp.1392 – 1404.
[20]	MC-T. Chao, S. Wang, S. T. Chakradhar, K. T. Cheng, “Response shaper: a novel technique to enhance unknown tolerance for output response compaction,” Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference, Nov 2005, pp. 80 – 87.
[21]	D. K. Weng, J. C. Rau, and C. H. Lin, “Optimal unknown bit filtering for test response masking,” Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium, July 2012, pp. 787-791.