最近以來，在掃描測試上實現低功率一直是個挑戰。先前有許多的研究都是著重在降低移動功率，只有少部分的研究有考慮到捕捉功率。在捕捉測試結果時，大量的切換動作會產生電源電壓降，進而導致電路故障與測試良率損失。本篇論文將提出一種新的演算法，並配合時脈閘的技術來閘控部分的掃描元件以防止內部電路產生不必要的切換動作。這些掃描元件都被劃分為若干個群組；對於每一個測試向量而言，在捕捉期間只有一部分的群組會對測試結果做存取的動作。我們所提出方法對於錯誤涵蓋率與測試時間不會造成任何影響，只是會增加一小部分的電路面積。經由ISCAS’89測試電路的實驗結果可知捕捉功率最大可以減少將近55%。
關鍵字: 時脈閘控、掃描測試、低功率

Recently, low power implementation is a great challenge in scan-based testing. Many previous researches are focus on shift power reduction, only a few are taking capture power into consideration. In capture mode, excessive IP-drop may occurred due to the high switching activity thus lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response in single capture cycle. The proposed method can reduce the capture power dissipation without any influence on fault coverage or testing time, and with a little impact on circuit area. Experimental results for ISCAS’89 benchmark circuits show that the capture power reduction in test sequence approximately can up to 55%.

中文摘要...I
英文摘要...II
Table of Contents...III
List of Figures...V
List of Tables...VI
	
	
CHAPTER 1 INTRODUCTION...1	
1.1 Motivation...1
1.2 The Challenges of Low Power Testing...3
1.3 Low Power Testing Techniques...4
1.3.1 ATPG-based...5
1.3.2 DFT-based...7
	
CHAPTER 2 BACKGROUND AND PRELIMINARIES...10
2.1 Full-Scan Architecture...10
2.2 Power Dissipation and Power Issues...12
	
CHAPTER 3 PORPOSED METHODS...17
3.1 Impact Function...17
3.2 Proposed Scan Architecture...21
3.3 Proposed Algorithm...23
3.3.1 Output-selection for each fault...26
3.3.2 Fault dropping...26
3.3.3 Gated scan cell selection...29

CHAPTER 4 EXPERIMENTAL RESULTS...33
	
CHAPTER 5 CONCLUSIONS AND FUTURE WORK……	39	
5.1 Conclusions...39
5.2 Future Work...39
	
REFERENCES...40
	
Appendix...45


LIST OF FIGURES
Figure 1.1 Shift power and capture power during scan testing...2
Figure 2.1 Difficulty of detecting stuck-at-faults in a sequential circuit...10
Figure 2.2 (a) A muxed-D scan cell (b) A sample scan chain...11
Figure 2.3 Conventional full-scan designed circuit...12
Figure 2.4 Dynamic power dissipation in a CMOS logic gate...13
Figure 2.5 Illustration of manufacturing yield loss...15
Figure 2.6 Example of weighted transition count...16
Figure 3.1 Example circuit...20
Figure 3.2 Proposed scan architecture...21
Figure 3.3 Architecture of gated clock controller...22
Figure 3.4 Timing diagram...22
Figure 3.5 Algorithm of scan cell grouping...24
Figure 3.6 Output selection (a) PO is exist for fault f   (b) PO is not exist for fault f...26
Figure 3.7 Procedure of fault dropping (a)is an essential fault (b)is a remaining fault...27
Figure 3.8 Algorithm of selecting gated scan cells...28
Figure 3.9 Matrix A and matrix TR...30
Figure 3.10 Procedure of gated scan cell selection...30
Figure 3.11 Bit reassignment to matrix A...31
Figure 3.12 Flow chart of the scan cell grouping procedure...32
Figure 4.1 Reduction of WTC in each capture cycle on s1423...35
Figure 4.2 Reduction of WTC in each capture cycle on s5378...36
Figure 4.3 Reduction of WTC in each capture cycle on s9234...36
Figure 4.4 Reduction of WTC in each capture cycle on s13207...37
Figure 4.5 Reduction of WTC in each capture cycle on s15850...37
Figure 4.6 Reduction of WTC in each capture cycle on s38417...38
Figure 4.7 Reduction of WTC in each capture cycle on s38584...38

LIST OF TABLES
Table 4.1 Experimental result of the seven large benchmarks on amount of 16 clusters...34
Table 4.2 Comparison between the method in [6] and the proposed method...34

[1] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,” in Proc. IEEE VLSI Test Symp. (VTS’93), Atlantic City, NJ, USA, Apr. 6-8, 1993, pp. 4-9
[2] P. Girad, “Survey of Low-Power Testing of VLSI Circuits,” IEEE Design & Test of Computers, vol. 19, no. 3, May/June, 2002, pp. 82-92.
[3] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, San Francisco: Elsevier, 2006
[4] X. Wen, K. Miyase, T. Suzuki, Y. Yamato, S. Kajihara, L.-T. Wang, and K. Saluja, “A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation,” in Proc. IEEE Int’l International Conference on Computer Design (ICCD’06), San Jose, CA, USA, Oct. 1-4, 2006, pp. 251-258
[5] S. Wang and S. K. Gupta, “DS-LFSR: A New BIST TPG for Low Heat Dissipation,” in Proc. IEEE Int’l Test Conf. (ITC’97), Washington, DC, USA, Nov. 1-6, 1997, pp. 848-857.
[6] P. Rosinger, B. M. Al-Hashimi, and N. Nicolici. “Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no.7, Jul. 2004. pp. 1142-1153
[7] S. Gerstendorfer and H. J. Wunderlich, “Minimized Power Consumption for Scan-Based BIST,” in Proc. IEEE Int’l Test Conf. (ITC’99), Atlantic City, NJ, USA, Sept. 28-30, 1999, pp. 77-84. 
[8] X. Wen, S. Kajihara, K. Miyase, T. Suzuki, K. Saluja, L.-T. Wang, K. Abdel-Hafez, and K. Kinoshita, “A New ATPG Method for Efficient Capture Power Reduction during Scan Testing,” in Proc. IEEE VLSI Test Symp. (VTS’06), Berkeley, CA, USA, Apr, 2006, pp.58-63
[9] R. Sankaralingam, R. R. Oruganti, and N. A. Touba. “Static Compaction Techniques to Control Scan Vector Power Dissipation,” in Proc. IEEE VLSI Test Symp. (VTS’00), Montreal, QC, Canada, Apr. 30-May. 4, 2000, pp. 35-40
[10] R. Sankaralingam and N. A. Touba, "Controlling Peak Power during Scan Testing," in Proc. IEEE VLSI Test Symp. (VTS’02), Apr. 28-May. 2, 2002. pp.153-159 
[11] S. Wang and S. K. Gupta, “ATPG for Heat Dissipation Minimization during Test Application,” IEEE Trans. Computers, vol. 47, no. 2, Feb. 1998, pp. 256-262.
[12] S. Wang and S. K. Gupta, “ATPG for Heat Dissipation Minimization for Scan Testing,” in Proc. ACM/IEEE Design Auto. Conf. (DAC’97), New York, NY, USA, 1997, pp. 614-619.
[13] S. Chakravarty and V. Dabholkar, “Minimizing Power Dissipation in Scan Circuits during Test Application,” in Proc. IEEE Asian Test Symp. (ATS’94), Nara, Japan, Nov 15-17, 1994, pp. 51-56.
[14] P. Girard, C. Landrault, S. Pravossoudovitch and D.Severac, “Reducing Power Consumption during Test Application by Test Vector Ordering,” in Proc. Int’l Circuits and Systems Symp. (ISCAS’98), vol. 2, Monterey, CA, USA, May. 31-Jun. 3, 1998, pp. 296-299.
[15] P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A Test Vector Ordering Technique for Switching Activity Reduction during Test Operation,” in Proc. Great Lakes Symp. on VLSI (GLS-VLSI’ 99), Ypsilanti, MI, USA, Mar. 4-6, 1999, pp. 24-27.
[16] W.-D. Tseng and L.-J. Lee, “Reduction of Power Dissipation during Scan Testing by Test Vector Ordering,” IEEE 8th Int’l Workshop on Microprocessor Test & Verification. (MTV’07), Austin, TX, USA, Dec. 4-6, 2007
[17] K. Miyase and S. Kajihara, “XID: Don’t Care Identification of Test Patterns for Combinational Circuit,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 2, Feb. 2004. pp.321-326
[18] X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K. Saluja, and K. Kinoshita, “On Low-Capture-Power Test Generation for Scan Testing,” in Proc. IEEE VLSI Test Symp. (VTS’05), Palm Springs, CA, USA, May. 1-5, 2005, pp. 265-270.
[19] X. Wen, Y. Yamashita, S. Morishima, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, “Low-Capture-Power Test Generation for Scan-Based At-Speed Testing,” in Proc. IEEE Int’l Test Conf. (ITC’05), Austin, TX, USA, Nov 8-10, 2005. pp 1-10.
[20] N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H.-J. Wunderlich, “Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics,” in Proc. Design & Test of Integrated Systems in Nanoscale Technology. (DTIS’06), Tunis, Tunisia, Sept. 5-7, 2006, pp. 359-364
[21] V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. M. Reddy, “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits during Test Application,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, Dec. 1998, pp. 1325-1333
[22] W.-D. Tseng, “Scan Chain Ordering Technique for Switching Activity Reduction during Scan Test,” IEE Proceedings on Computers and Digital Techniques, vol. 152, no. 5, Sept. 2005, pp. 609-617.
[23] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and A. Virazel, “Design of Routing-Constrained Low Power Scan Chains,” in Proc. Design Automation and Test in Europe conference and exhibition, Paris, France, Feb 16-20, 2004, pp. 62-67.
[24] L. Whetsel, “Adapting Scan Architectures for Low Power Operation,” in Proc. IEEE Int’l Test Conf. (ITC’00), Atlantic City, NJ, USA, Oct. 3-5, 2000, pp. 863-872.
[25] J. Saxena, K. M. Butler, and L. Whetsel, “An Analysis of Power Reduction Techniques in Scan Testing,” in Proc. IEEE Int’l Test Conf. (ITC’01), Baltimore, MD, USA, Oct. 30-Nov. 1, 2001, pp. 670-677.
[26] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, “A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores,” in Proc. IEEE Asian Test Symp. (ATS’01), Kyoto, Japan, Nov 19-21, 2001, pp. 253-258.
[27] T.-C. Huang and K.-J. Lee, “A Token Scan Architecture for Low-Power Testing,” in Proc. IEEE Int’l Test Conf. (ITC’01), Baltimore, MD, USA, Oct. 30-Nov. 1, 2001, pp 661-669. 
[28] N. Nicolici and B. M. Al-Hashimi, “Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits,” IEEE Trans. Computers, vol. 51, no. 6, Jun. 2002, pp. 721-734
[29] R. Sankaralingam and N. A. Touba, “Reducing test power during test using programmable scan chain disable,” in Proc. The First IEEE International Workshop on Electronic Design, Test and Applications. (DELTA’02), Christchurch, New Zealand, Jan. 29-31, 2002, pp.159-163.
[30] S. Gerstendorfer and H.-J. Wunderlich, “Minimized Power Consumption for Scan-Based BIST,” in Proc. IEEE Int’l Test Conf. (ITC’01), Atlantic City, NJ, USA Sept. 28-30, 1999, pp. 77-84.
[31] R. Sankaralingam and N. A. Touba, “Inserting Test Points to Control Peak Power During Scan Testing”, in Proc. IEEE Int’l Symp. Defect and Fault Tolerance in VLSI Systems. (DFT’02), Vancouver, Canada, Nov. 6-8, 2002, pp. 138-146.
[32] T.-C. Huang and K.-J. Lee, “Reduction of Power Consumption in Scan-Based Circuits during Test Application by an Input Control Technique,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, Jul. 2001, pp. 911-917.
[33] E. Alpaslan, Y. Huang, X. Lin, W.-T. Cheng, J. Dworak, “Reducing Scan Shift Power at RTL,” in Proc. IEEE VLSI Test Symp. (VTS’08), San Diego, CA, USA, Apr. 27-May. 1, 2008, pp. 139-146
[34] K. J. Lee, T. C. Huang, and J. J. Chen, “Peak-power reduction for multiple-scan circuits during test application,” in Proc. IEEE Asian Test Symp. (ATS’00), Taipei, Taiwan, Dec. 4-6, 2000, pp.453-458.
[35] C.-Y. Wang and K. Roy, “Maximum Power Estimation for CMOS Circuits Using Deterministic and Statistical Approaches,” IEEE Transactions on VLSI Systems, vol. 6, no. 1, Mar. 1998, pp. 134-140.
[36] C. Kim and S.-M. Kang, “A Low-Swing Clock Double-Edge Triggered Flip-Flop,” IEEE J. Solid-State Circuits, vol. 37, no. 5, May. 2002, pp.648-652.
[37] N. Jha and S. Gupta, Testing of digital systems, Cambridge University Press, 2003.
[38] N. Nicolici and X. Wen, “Embedded Tutorial on Low Power Test,” in Proc. European Test Symp. (ETS' 07), Freiburg, Germany, May. 20-24, 2007, pp. 202-207.
[39] H. K. Lee and D. S. Ha, “Atalanta: an Efficient ATPG for Combinational Circuits,” Technical Report, 93-12, Dep't of Electrical Eng., Virginia Polytechnic Institute and State University, Blacksburg, Virginia, 1993.
[40] H. K. Lee and D. S. Ha, “HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 9, Sept. 1996, pp. 1048–1058