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系統識別號 U0002-1407200813292300
中文論文名稱 新式的掃描鏈時脈閘以降低捕捉功率
英文論文名稱 A New Scan Chain Clock Gating for Capture Power Reduction
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 96
學期 2
出版年 97
研究生中文姓名 吳忠霖
研究生英文姓名 Chung-Lin Wu
學號 695450402
學位類別 碩士
語文別 英文
口試日期 2008-06-18
論文頁數 52頁
口試委員 指導教授-饒建奇
委員-李建模
委員-梁新聰
中文關鍵字 時脈閘控  掃描測試  低功率 
英文關鍵字 Clock gating  scan testing  low power 
學科別分類 學科別應用科學電機及電子
中文摘要 最近以來,在掃描測試上實現低功率一直是個挑戰。先前有許多的研究都是著重在降低移動功率,只有少部分的研究有考慮到捕捉功率。在捕捉測試結果時,大量的切換動作會產生電源電壓降,進而導致電路故障與測試良率損失。本篇論文將提出一種新的演算法,並配合時脈閘的技術來閘控部分的掃描元件以防止內部電路產生不必要的切換動作。這些掃描元件都被劃分為若干個群組;對於每一個測試向量而言,在捕捉期間只有一部分的群組會對測試結果做存取的動作。我們所提出方法對於錯誤涵蓋率與測試時間不會造成任何影響,只是會增加一小部分的電路面積。經由ISCAS’89測試電路的實驗結果可知捕捉功率最大可以減少將近55%。
關鍵字: 時脈閘控、掃描測試、低功率
英文摘要 Recently, low power implementation is a great challenge in scan-based testing. Many previous researches are focus on shift power reduction, only a few are taking capture power into consideration. In capture mode, excessive IP-drop may occurred due to the high switching activity thus lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response in single capture cycle. The proposed method can reduce the capture power dissipation without any influence on fault coverage or testing time, and with a little impact on circuit area. Experimental results for ISCAS’89 benchmark circuits show that the capture power reduction in test sequence approximately can up to 55%.
論文目次 中文摘要...I
英文摘要...II
Table of Contents...III
List of Figures...V
List of Tables...VI


CHAPTER 1 INTRODUCTION...1
1.1 Motivation...1
1.2 The Challenges of Low Power Testing...3
1.3 Low Power Testing Techniques...4
1.3.1 ATPG-based...5
1.3.2 DFT-based...7

CHAPTER 2 BACKGROUND AND PRELIMINARIES...10
2.1 Full-Scan Architecture...10
2.2 Power Dissipation and Power Issues...12

CHAPTER 3 PORPOSED METHODS...17
3.1 Impact Function...17
3.2 Proposed Scan Architecture...21
3.3 Proposed Algorithm...23
3.3.1 Output-selection for each fault...26
3.3.2 Fault dropping...26
3.3.3 Gated scan cell selection...29

CHAPTER 4 EXPERIMENTAL RESULTS...33

CHAPTER 5 CONCLUSIONS AND FUTURE WORK…… 39
5.1 Conclusions...39
5.2 Future Work...39

REFERENCES...40

Appendix...45


LIST OF FIGURES
Figure 1.1 Shift power and capture power during scan testing...2
Figure 2.1 Difficulty of detecting stuck-at-faults in a sequential circuit...10
Figure 2.2 (a) A muxed-D scan cell (b) A sample scan chain...11
Figure 2.3 Conventional full-scan designed circuit...12
Figure 2.4 Dynamic power dissipation in a CMOS logic gate...13
Figure 2.5 Illustration of manufacturing yield loss...15
Figure 2.6 Example of weighted transition count...16
Figure 3.1 Example circuit...20
Figure 3.2 Proposed scan architecture...21
Figure 3.3 Architecture of gated clock controller...22
Figure 3.4 Timing diagram...22
Figure 3.5 Algorithm of scan cell grouping...24
Figure 3.6 Output selection (a) PO is exist for fault f (b) PO is not exist for fault f...26
Figure 3.7 Procedure of fault dropping (a)is an essential fault (b)is a remaining fault...27
Figure 3.8 Algorithm of selecting gated scan cells...28
Figure 3.9 Matrix A and matrix TR...30
Figure 3.10 Procedure of gated scan cell selection...30
Figure 3.11 Bit reassignment to matrix A...31
Figure 3.12 Flow chart of the scan cell grouping procedure...32
Figure 4.1 Reduction of WTC in each capture cycle on s1423...35
Figure 4.2 Reduction of WTC in each capture cycle on s5378...36
Figure 4.3 Reduction of WTC in each capture cycle on s9234...36
Figure 4.4 Reduction of WTC in each capture cycle on s13207...37
Figure 4.5 Reduction of WTC in each capture cycle on s15850...37
Figure 4.6 Reduction of WTC in each capture cycle on s38417...38
Figure 4.7 Reduction of WTC in each capture cycle on s38584...38

LIST OF TABLES
Table 4.1 Experimental result of the seven large benchmarks on amount of 16 clusters...34
Table 4.2 Comparison between the method in [6] and the proposed method...34



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