帶通三角積分調變器廣泛的應用在中頻與射頻的通訊系統中。為了避免在zero IF 接收器的低頻雜訊和預防電路的不對稱性所造成的接受機性能變差，單一中頻架構的接收器是一個很好的選擇。訊號從接收端進來，然後降頻下來，因為製程變異有可能造成訊號變異，此時可調式帶通三角積分調變器是必須的，可以增加接收器的效能。連續時間的三角積分調變器可以藉著調整運算放大器的轉導來改變調變器的中心頻率。然而使用可調的連續時間三角積分調變器的電路，需要比較複雜的技術及額外的金錢。
因為電容誤差的比例較小，所以離散時間的三角積分調變器廣泛地被應用在窄頻寬的資料的轉換器。在本論文中，可調式帶通三角積分調變器使用一個變數來改變中心頻率來使調變器的效能更加完美。為了達到一個調變器中可調的調諧電器，必須利用複數的離散時間的訊號路徑來達到改變中心頻率的目的。為了達到中心頻率從五百萬赫茲改變到三千萬赫茲的大改變，電路的複雜性將會增加。
本論文提出一個可調式雙倍取樣帶通三角積分調變器，藉由外部的一個輸入來改變中心頻率。中心頻率可以從五百萬赫茲改變到三千萬赫茲在取樣頻率七千萬赫茲下。它的性能可能因此被透過微調中心頻率改進。這個調變器將使用製程為TSMC 0.35um 2P4M 實現。整體佈局面積為2.8×1.5 mm2。量測到的信號的動態範圍在二十萬赫茲頻寬下為68dB。電路整體的功率消耗為58mW 在供應電壓3.3V 下。

A Bandpass ∆Σ modulators are widely used in inter-mediate frequency (IF) and radio frequency (RF) communication systems. In order to avoid the low frequency noise in zero IF receiver and prevent the mismatch of the circuits from degrading the receiver performance, the single IF architecture is a good candidate. Since the signal, which is received and down-converted, may be varied due to process variations, a tunable bandpass ∆Σ modulator is required to improve the performance of the receiver. There are so many efforts are devoted in tunable continuous-time (CT) ∆Σ modulator by the modifying the transconductance of OTA in the resonator. However, an elaborate tuning scheme and an additional cost are demanded in the tunable continuous-time ∆Σ modulator.
Since the mismatch among capacitors is very small, the SC ∆Σ modulators are popular in narrow band data converter. In this paper, a tunable bandpass ∆Σ modulator by one parameter only is adopted to optimize modulator performance. To achieve a tunable resonator in the modulator, a multiple path SC scheme is applied for the adjustments of the center frequency. A wide tuning range from 5MHz to 30MHz is preformed to demonstrate the flexibility of the modulator. Furthermore, a double sampling technique is used to relax the requirements of opamp performance.
A tunable switched-capacitor (SC) bandpass delta sigma (∆Σ) modulator using double sampling by one input parameter is proposed. The center frequency of the modulator can be varied from 5MHz to 30MHz at a sampling frequency of 70MHz. Its performance can be hence improved by fine tuning the center frequency. The purposed modulator was implemented in 0.35-µm 2P4M CMOS standard technology with the core area of 2.8×1.5 mm2. The measured dynamic range of 68dB within 200 kHz bandwidth can be achieved. Its power consumption is 58mW under a 3.3-V supply voltage.

Table of Contents
CHAPTER 1 INTRODUCTION……………………………………………………...1
1.1 Motivation…………………………………………………………………..1
1.2 Organization………………………………………………………………...2
CHAPTER 2 FUNDAMENTALS OF ∆Σ MODULATOR…………………………...3
2.1 Introduction…………………………………………………………………3
2.2 Quantization Noise………………………………………………………….3
2.3 Oversampling Technique……………………………………………………9
2.4 Noise-Shaped ∆Σ Modulator………………………………………………14
2.4.1 First-Order ∆Σ Modulator…………………...……………………17
2.4.2 Second-Order ∆Σ Modulator……………………………………...21
2.5 High-Order ∆Σ Modulators………………………………………………..23
2.5.1 Single-Loop High-Order ∆Σ Modulators…………………………25
2.5.2 Multi-Stage Noise Shaping ∆Σ Modulators………………………28
2.6 Performance Metrics………………………………………………………31
2.7 Summary…………………………………………………………………..34
CHAPTER 3 DESIGN OF THE DOUBLE SAMPLING BANDPASS ∆Σ
MODULATOR WITH THE TUNABLE CENTER FREQUENCY…..35
3.1 Introduction………………………………………………………………..35
3.2 The Fundamental of Bandpass ∆Σ Modulators……………………………36
3.2.1 The Fundamental of the Second-Order Bandpass ∆Σ Modulator...36
3.2.2 The Fundamental of the Fourth-Order Bandpass ∆Σ Modulator…38
3.3 The Architecture of the Double Sampling Bandpass ∆Σ Modulator with the
Center Frequency………………………………………………………….40
3.3.1 The Algorithm of the Double Sampling Bandpass ∆Σ Modulator
with the Center Frequency……………………………………….40
3.3.2 The Tunable Resonator of the Double Sampling Bandpass ∆Σ
Modulator with the Center Frequency……………………………41
3.4 The Matlab Simulation of the Bandpass ∆Σ Modulator with the Tunable
Center Frequency………………………………………………………..42
CHAPTER 4 Implementation of the Double Sampling Bandpass ∆Σ Modulator with
the Tunable Center Frequency…………………………………………45
4.1 Introduction………………………………………………………………..45
4.2 Double Sampling Tunable Bandpass Resonator…………………………..45
4.3 Clock Generator…………………………………………………………...48
4.4 Gain-Boosted Folded-Cascode Amplifier…………………………………48
4.5 Double Sampling Bandpass ∆Σ Modulator with the Tunable Center
Frequency………………………………………………………………….49
CHAPTER 5 Simulation and Measurement Results………………………………....51
5.1 Introduction……………..…………………………………………………51
5.2 Simulation of the Gain-Boosted Folded-Cascode Amplifier……………...51
5.3 Simulation of the Double Sampling Bandpass Delta-Sigma Modulator with
the Tunable Center Frequency……………………………………………..53
5.4 Measurement Result……………………………………………………….56
CHAPTER 6 CONCLUSIONS………………………………………………………59
6.1 Conclusion…………………………………………………………………59
6.2 Future Work………………………………………………………………..59
List of Figures
Figure 2.1 Two forms of quantization (a) midtread and (b) midrise…………………..4
Figure 2.2 The quantizer and its linear model…………………………………………5
Figure 2.3 The probability density function for the quantization error………………..6
Figure 2.4 The power spectral density of quantization noise………………………….7
Figure 2.5 Oversampled A/D conversion with simple quantization and
down-sampling…………………………………………………………….10
Figure 2.6 (a) A simplified oversampled A/D conversion (b) the magnitude frequency
response of the low-pass filter……………………………………………11
Figure 2.7 Quantization-noise power spectral density of Nyquist and oversampling
rate conversion…………………………………………………………...13
Figure 2.8 Block diagram of an oversampling ∆Σ A/D converter…………………...15
Figure 2.9 (a) A general ∆Σ modulator and (b) linear model of the ∆Σ modulator…..16
Figure 2.10 A first-order oversampled ∆Σ modulator………………………………..18
Figure 2.11 The power spectral density of a first-order oversampled ∆Σ modulator...21
Figure 2.12 A second-order oversampled ∆Σ modulator…………………………….23
Figure 2.13 The power spectral density of a second-order oversampled ∆Σ
modulator……………………………………………………………….23
Figure 2.14 A block diagram of a fifth-order ∆Σ modulator with distributed
feedback………………………………………………………………...27
Figure 2.15 Block diagram of a cascade analog-to-digital modulator……………….29
Figure 2.16 Nonideal transfer curve of a multi-level quantizer……………………...31
Figure 2.17 SNR and SNDR vs. input power………………………………………..34
Figure 3.1 The single IF Architecture………………………………………………..36
Figure 3.2 (a) Lowpass prototype (b) Bandpass prototype…………………………..37
Figure 3.3 A second-order bandpass ∆Σ modulator………………………………….38
Figure 3.4 A fourth-order bandpass ∆Σ modulator…………………………………...39
Figure 3.5 In-band noise level versus Oversampling ratio…………………………...40
Figure 3.6 The tunable bandpass resonator…………………………………………..42
Figure 3.7 The architecture of the presented bandpass ∆Σ modulator……………….43
Figure 3.8 Matlab Simulation(a) α = 0 (b) α = 0.9 (b) α = - 0.9………………….…44
Figure 4.1 (a) The presented resonator with tunable center frequency………………47
(b) its corresponding clocks……………………………………………...47
Figure 4.2 The presented double sampling bandpass ∆Σ modulator with tunable center
frequency…………………………………………………………………50
Figure 5.1 (a) opamp circuit (b) CMFB circuit………………………………………51
Figure 5.2 SNR simulation (a) when α = 0.9 (b) when α = -0.9…………………….54
Figure 5.3 Simulation of the input dynamic range…………………………………...55
Figure 5.4 Die photo of the presented modulator…………………………………….55
Figure 5.5 Test step…………………………………………………………………..57
Figure 5.6 AWG420 Arbitrary Waveform…………………………………………...57
Figure 5.7 Agilent infiniium 54833D………………………………………………...57
Figure 5.8 PCB board of the presented ADC…………………………………….......58
Figure 5.9 The output spectrum of the presented ADC……………………………...58
List of Tables
Table 3.1 The summary of lowpass versus bandpass ∆Σ modulators………………..39
Table 4.1 Summary of the Opamp Performance……………………………………..49
Table 5.1 Simulation of the Opamp Performance……………………………………51
Table 5.2 Performance Summary of the Double Sampling Bandpass ∆Σ Modulator
with Tunable Center Frequency…………………………………………...56

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