第二代通訊標準已經在全球使用許久，其中以GSM系統最為普遍。由於市場壓力，許多第二代之通訊技術已慢慢更進一步延伸，在需求上要求更高的系統容量和資料率，所以第三代無線通訊技術的WCDMA因此產生，它可以提供更高的頻寬，以符合各式多媒體與無線寬頻需求，所著重的一點就是它比起原本的第二代GSM無線通訊系統，大幅改進了無線部分的多工技術，使得我們可以在有限的無線通訊頻帶中，透過更新的無線傳輸技術來提供更為豐富與大量的使用者資料。其中類比/數位轉換器是無線接收端的核心電路，而超取樣和ΣΔ調變技術則是早已被應用於現代超大型積體電路中的類比數位轉換介面。有別於傳統的Niquist 類比/數位轉換器需要高精確的取樣電路，超取樣ΣΔ調變技術對電路上的雜訊敏感度低，這使得它可以實現於較低成本的標準數位製程中，有效的降低成本並進一步結合類比和數位電路以達到系統整合(SOC)的目標。

    配合著無線通信的進步，在系統上要作到高速高解析度的類比/數位轉換器需要高取樣頻率。在考量低功率低電壓的前提下，這對一般切換電容電路而言是一大限制，因為切換電容電路上中的高阻抗開關會限制訊號的大小和取樣頻率，儘管有些電路技巧如boot- strapping switch 和 switched- opamp可以克服這些問題，但這些電路技巧在設計上更為複雜困難並仍然受限於取樣頻率的問題。以連續時間電路來設計，可以避開這些限制達到高速高解析度的目標，並且不會有一般切換電容電路的缺點(Input-signal sampling errors, Settling-time errors)。

    本論文所要研究的方向為設計一個適用於WCDMA架構下之低通和差積分調變器，我們使用連續時間電路來設計，脈衝非時變轉換被使用來將離散時間濾波器轉移函式轉換為連續時間濾波器轉移函式，連續時間積分器使用主動式電阻電容(active-RC)電路來實現，電路架構用單一回授路徑方式，多位元nonreturn-to-zero (NRZ)數位類比轉換器作回授以降低對clock jitter的敏感度。據此，我們使用0.18微米1P6M標準製程設計了一個連續式低通三角調變器，其工作電壓為1.8V，取樣頻率52MHz，超取樣比為13，模擬結果顯示在頻寬為2MHz及取樣頻率52MHz下其動態輸入範圍為75dB，而最大的訊號雜訊失真比為72dB，此時輸入訊號450mV，有效解析度12bits，總功率消耗6mW。

The 3rd generation mobile communications standard (WCDMA), based on a wideband code division multiple access (W-CDMA) modulation scheme, will be available in the commercial market. The use of spread spectrum techniques requires high-speed baseband circuits (few MHz) with a moderate dynamic range (10~12 bit). A basic building block of such a WCDMA receiver is an analog-to-digital converter. Over-sampling and sigma-delta modulation techniques are used in the analog to digital conversion interface of modern very large scaled integrated circuits. Unlike Nyquist rate A/D converters, which need high-precision building blocks, A/D converters show low sensitivity to circuit imperfections. This technique is then well-suited for standard low-cost CMOS technologies dedicated to digital VLSI circuits.

    The recent high demand for wideband, high resolution A/D converters for telecommunication applications requires very high sampling frequencies. The continuously decreasing supply voltage of recent CMOS technologies is causing important limitations to the performances of SC circuits. High switch resistance limits the signal dynamic range and limits the sampling frequency. Some circuit techniques, like bootstrapping switch and switched-opamp, have been developed to overcome this problem. These techniques are rather complex and still limit the sampling frequency. Continuous-time (CT) circuits do not suffer from these limitations and are therefore capable of achieving higher performances in recent low-voltage CMOS processes. Input-signal sampling errors, like settling-time errors and charge injection, are other discrete-time (DT) problems that do not exist in CT circuits.

   In this thesis, we try to design a continuous-time low-pass sigma-delta modulator suitable for WCDMA application. The impulse time invariant transformation is used to transfer the discrete time filter transfer function to the continuous-time filter transfer function. The continuous-time modulator uses Active-RC Integrators circuits to fulfill the implementation. Our circuit architecture is with single-loop, and the multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivities.

   The operating voltage of our proposed low-pass sigma-delta modulators for WCDMA receiver application is 1.8V；the sampling frequency is 52MHz, and the oversampling ratio is 13. The simulation results show that the bandwidth is 2MHz；the sampling frequency is 52MHz；the dynamic input range is 75dB, and the maximum signal to noise ratio is 72 dB. Its input signal is 0.45V；the effective resolution is 12bits, and the total power dissipation is 6mW.

Contents

CHAPTER 1 INTRODUCTION …………………………………………1  

1.1 Motivation and Applications………………………………1
1.1.1 Zero-IF Receiver Architecture…………………………3
1.1.2 ADC Dynamic Range Specification………………………6

CHAPTER 2 Overview of Delta-Sigma Modulator………………9

2.1 Quantization Noise …………………………………………9
2.1.1 Quantization Error with Oversampling………………11
2.1.2 Noise-Shaped Delta-Sigma Modulator…………………14
2.1.2 First-Order Delta-Sigma Modulator …………………15
2.1.3 Multi-Bit Sigma-Delta Modulator ……………………16
2.2 Continuous-Time Versus Discrete-Time ΣΔ Modulator…19
2.3 Continuous-Time Design and Impulse-Invariant Transform ………………………………………………………………………23
2.3.1 Impulse-Invariant transform …………………………23
2.3.2 NRZ Transformation………………………………………26

CHAPTER 3 SYSTEM DESIGN ………………………………………29

3.1 Power-Efficient Modulator Implementation……………29
3.2 Analysis of Non-Ideal Effects …………………………32
3.2.1 Integrator Non-Idealities ……………………………33
3.2.2 Temporal Non-Idealities ………………………………39
3.2.3 Other Non-Idealities……………………………………42
3.3 Modulator Architecture Design …………………………43


CHAPTER 4 CIRCUIT IMPLEMENTATION……………………………46

4.1 Modulator Design……………………………………………46
4.2 Integrator Design …………………………………………48
4.3 Quantizer Design……………………………………………51
4.3.1 Comparator Design ………………………………………52
4.4 DAC Design……………………………………………………54
4.4.1 Current Steering DAC Cell Design……………………56
4.5 Layout…………………………………………………………57
4.6 Simulation Result …………………………………………59
4.7 Summary ………………………………………………………61

CHAPTER 5 CONCLUSIONAND FUTURE WORK ………………………62

5.1 Conclusion……………………………………………………62
5.2 Future Work …………………………………………………62

REFERENCE …………………………………………………………64

Table of Contents
CHAPTER 1 INTRODUCTION…………………..……………………….1
1.1 Motivation and Applications …………………………………………………………...1
1.1.1 Zero-IF Receiver Architecture ………….………………………………………….3
1.1.2 ADC Dynamic Range Specification ………………………………………………..6
CHAPTER 2 Overview of Delta-Sigma Modulator ………….………..9
2.1 Quantization Noise ……………………………………………………………………..9
2.1.1 Quantization Error with Oversampling …………………………………………11
2.1.2 Noise-Shaped Delta-Sigma Modulator ….……………………………………..14
2.1.2 First-Order Delta-Sigma Modulator …….…………………………………..….15
2.1.3 Multi-Bit Sigma-Delta Modulator ………………………………………………..16
2.2 Continuous-Time Versus Discrete-Time Σ∆ Modulator ………………………....…....19
2.3 Continuous-Time Design and Impulse-Invariant Transform …………………...…...23
2.3.1 Impulse-Invariant transform ……………………………………………………...23
2.3.2 NRZ Transformation ………………………………………………..……………26
CHAPTER 3 SYSTEM DESIGN …………………………………………29
3.1 Power-Efficient Modulator Implementation ………………..………………………...29
3.2 Analysis of Non-Ideal Effects …………..……………………………….……………32
3.2.1 Integrator Non-Idealities …………………………………………………………33
3.2.2 Temporal Non-Idealities…………………………………………………………39
3.2.3 Other Non-Idealities……………………………………………………….….42
3.3 Modulator Architecture Design …………………………………………….…………43
VII
CHAPTER 4 CIRCUIT IMPLEMENTATION……….………………46
4.1 Modulator Design ………………………………………………………...…………46
4.2 Integrator Design …………………………………………………………...…………48
4.3 Quantizer Design …………………...……………………………………...………….51
4.3.1 Comparator Design ………...…………………………………………….……...52
4.4 DAC Design ………………………...……….……....………………………………..54
4.4.1 Current Steering DAC Cell Design …………...………………………….……..56
4.5 Layout ……………………………….…………………………………………..…57
4.6 Simulation Result ……….……………….……………………………………………59
4.7 Summary ..………………………………….…………………………………..……61
CHAPTER 5 CONCLUSIONAND FUTURE WORK ………...…62
5.1 Conclusion ……………………………………………………………………….62
5.2 Future Work ……………………………………………………………...…………62
REFERENCE …………………………………………………..………….…64
VIII
List of Figures
Fig. 1.1: Zero-IF receiver architecture for WCDMA ………………………………………3
Fig. 1.2: (a) Wanted signal and LO signal. (b) Perfect ZIF conversion. (c) Imperfect ZIF
conversion ……………………………………………………………………...4
Fig. 1.3: W-CDMA …………………………………………………………………………5
Fig. 2.1: Quantizer and its linear model. …………………………………………………...9
Fig. 2.2: The power spectral density of the quantization noise ……………………..…….10
Fig. 2.3: (a) A simplified oversampled A/D conversion and (b) the brick-wall. ………….13
Fig. 2.4: Quantization noise power spectral density of Nyqusit and oversampling rate
conversion ……………………………………………………………………...13
Fig. 2.5: (a) A general ∆Σ modulator ,(b) linear model of the ∆Σ modulator …………….14
Fig. 2.6: A first-order oversampled ∆Σ modulator ………………………………………..16
Fig. 2.7: A linear model of multi-bit modulator with DAC errors ………………………..17
Fig. 2.8: Power spectrum of DAC error …………………………………………………..18
Fig. 2.9: Discrete-time ∆Σ modulator …………………………………………………….19
Fig. 2.10: Continuous-time ∆Σ modulator ………………………………………………..20
Fig. 2.11: Mapping between the discrete-time and continuous-time system ……………..24
Fig. 2.12: NRZ, RZ, and HZ DAC feedback impulse responses …………………………25
Fig. 2.13: A continuous-time ∆Σ modulator ………………………………………………26
Fig. 3.1: General third single-bit CT ∆Σ modulator with weighted feedback ki …...……..31
Fig. 3.2: Simplified schematic of a fully different integrator with finite-loop gain A0 …...32
Fig. 3.3: Fully different integrator with frequency-dependent loop gain A0(s), excess phase
cancellation by Rz, and additional parasitic capacitances……………………….36
IX
Fig. 3.4: Simplified schematic of a fully different integrator with variations due to IC
manufacturing process in the employed resistors and capacitors. ……………..37
Fig. 3.5: DAC feedback impulse response RDAC,NRZ(t,τd) under the influence of excess loop
delay τd ………...……………………………………………………………… 39
Fig. 3.6: The pulse type of the NRZ feedback signal …………………….………...…….40
Fig. 3.7: Implemented 3bit third-order modulator architecture m………...………………43
Fig. 3.8: The System Simulation result of Continuous time ∆Σ Modulator …...……........45
Fig. 3.9: (a) The system simulated signal-to-RC mismatch noise ratio, (b) The system
simulated signal-to-jitter noise ratio .………...……………………………..45
Fig. 4.1: Simplified circuit diagram of the ∆Σ modulator …………………………...……46
Fig. 4.2: The System Simulation result of Continuous time ∆Σ Modulator ………...……47
Fig. 4.3: Simplified amplifier schematic ...………………………………………………..49
Fig. 4.4: AC simulation of the two-stage amplifier ……………………………………….50
Fig. 4.5: 3-bit quantizer …………………………………………………………………...51
Fig. 4.6: Differential SC comparator ……………………………………………………...52
Fig. 4.7 Latch-type Comparator …………………………………………………………..53
Fig. 4.8: Simplified feedback DAC topology …………………………………………… 55
Fig. 4.9: Current cell with cascaded transistor ….………………………………………...56
Fig. 4.10: Layout plan …………………………………………………………………….57
Fig. 4.11: Chip Layout …………………………………………………………………....58
Fig. 4.12: The circuit Simulation result of Continuous time ∆Σ Modulator ……………...59
Fig. 4.13: SNR versus input power ……………………………………………………….60
Fig. 4.14: Monte Carlo RC mismatch result ………………………………………….......60
X
List of Tables
Table 2.1 Main advantages of Continuous-time ∆Σ modulators over DT ∆Σ modulators..21
Table 2.2 Main disadvantages of Continuous-time compared DT ∆Σ modulators………..22
Table 4.1 Simulation Result Summary of the Third-Order ∆Σ Modulator………………60
Table 4.2: Performance summary of the state of the art ∆Σ Modulators………………….61

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