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系統識別號 U0002-1307200513204400
中文論文名稱 10位元低功率的數位類比轉換器
英文論文名稱 A 10bits Low Power Digital-to-Analog Converter
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 93
學期 2
出版年 94
研究生中文姓名 蔡仁杰
研究生英文姓名 Jen-Chieh Tsai
學號 692390445
學位類別 碩士
語文別 英文
口試日期 2005-06-09
論文頁數 53頁
口試委員 指導教授-郭建宏
委員-黃育賢
委員-陳建中
委員-陳淳杰
委員-江正雄
中文關鍵字 數位類比轉換器  電流鏡  低功率  小面積 
英文關鍵字 Digital to analog converter  current mirror  low power current-steering  small area 
學科別分類 學科別應用科學電機及電子
中文摘要 在現代通訊應用中,類比電路和數位資料的傳輸必須透過一些介面傳輸,而在大家都趨向於SOC的時代中,面積跟功率都成為一個重要的關鍵,而在一般的數位類比轉換器,速度都已經可以達到需求,不過在面積跟功率都還有挑戰的空間,針對這些問題,我們研究出了一種新的電流鏡切換方式,他不但可以顧到面積問題,並且在功率消耗中也可以達到低功率的要求,精準度也都可以達到我們所期望的。
Current-steering DAC的基本概念是利用電流源的方式,藉由選擇電路來使開關導通來將所需的電流切換至輸出,而Binary-weight DAC與其他架構比較起來current steering DAC具有較快的操作速度,但是以電流形式實現必須考慮以下非線性的特性:電流源的不匹配,電流源的有限輸出阻抗和負載電阻之非線性
當解析度越來越高時Binary-weighted DAC的monotonicity與glitch兩項問題將會越來越嚴重;相對地,當segmented DAC的解析度越來越大時,面臨Binary to Thermometer code decoder的複雜度與面積大幅提升,使得設計上越來越困難,且Binary to Thermometer code decoder的功率消耗也將很大。因此我們提出的triple segment DAC可以解決上述的問題,而且藉著這種混合的架構使得高解析度DAC的難度降低了許多。在10位元的轉換器中,10位元完全以segmented DAC來做為一個基本架構,並且使用了一個新型的電流鏡。如此不但節省了面積的浪費並且在功率上面獲得了很大的改進。此外採取外掛電阻的方式直接將輸出訊號由電流轉成電壓。
在電流源的部分共包含有三個部分,分別為參考電流源、負回授增益級與電流鏡輸出級,藉著負回授增益級,大大增加了電流鏡輸出級的阻抗與其和參考電流源間的匹配準確度,並且能夠使電路在負回授的穩定下,能夠準確的使電路快速穩定。因此對於之前討論的電流源不匹配與負載電阻之非線性兩大問題提供有效的解決方法。電流源架構的構想與gain-boosting的觀念類似,藉由負回授的增益級來提高由輸出電晶體所看到的輸出阻抗。
晶片的實現上,利用0.18 um CMOS 製程所研製。整個DAC的模擬,在10MHz時,其INL能收斂在+0.14LSB ~ -0.14LSB之間,DNL能收斂在+0.14LSB ~ -0.13LSB之間,整個DAC的步階響應,能收斂於0.1us以內,也就是能操作於10MHz,整體功率消耗為2.5mW。在晶片的模擬驗證上,證實了此架構的可行性。
英文摘要 A low-power digital-to-analog converter for portable electronics is introduced. A fully segmented architecture with a spike-free current mirror is presented to improve the INL/DNL and reduce the power consumption of the high-speed current steering DAC. The presented 10-bit DAC have been implemented in 0.18um 1P6M CMOS standard technology, and its core area is 0.27mm2. The simulation results show the DNL/INL is 0.14/0.14 at a conversion rate of 10MHz, and consume 2.5mW of power from a 1.8V supply voltage. There is a strong demand to promote the performance of the high-speed digital-to-analog converter (DAC) in many telecommunication systems, such as WLAN, AWG, and HDTV. The full segmented DAC is interested because of their fast operation speed, less consumed area, and high power efficiency. Many efforts have been devoted to improve the resolution and settling time for these current steering DACs.
The differential switch pair is popular to form the basic current switch in current cell of the segmented DAC. The output voltage of the current cell is hence stabilized while the current branch is cut off. However, a dummy load should be added at the other side of the differential switch to avoid this switch entering cut-off mode. Thus, an additional power would be wasted on this dummy path. Moreover, there are a couple of deglitch circuits are needed to suppressed the spike caused by the abnormal switching on these differential pairs. The extra hardware and their power consumption would be paid.
In this literature, a new high-accuracy current cell with spike-free switching for the full segmented current steering DAC is proposed. The output voltage of the current cell can be kept on a fixed voltage level with no other output path is needed while the current cell is turned off. The power dissipated on the dummy load in the conventional DAC can thus be excluded. Since no deliberated deglitch circuits in the proposed current steering circuit are required, less hardware and power would be achieved for a 10-bit full segmented DAC.

論文目次 Chapter 1 Introduction 1
Chapter 2 The Digital-to-Analog Converters Overview 5
2.1 Digital Code 5
2.2 Digital-to-Analog Converter Specifications 7
2.3 Converter Type 13
2.4 Classification of Digital-to-Analog Converter 14
2.4.1 Current division DACs 15
2.4.2 Voltage division DACs 19
2.4.3 Charge division DACs 21
2.5 Comparisons of DACs 24
Chapter 3 The 10-Bit Current-Steering DAC 25
3.1 Current Mirror Analysis 25
3.1.1 Current mirror circuit simulation results and comparisons 31
3.2 Mismatch Effect 33
3.2.1 Random error 33
3.2.2 Systematic and graded error 34
3.3 Partition Current-Steering DAC 35
3.3.1Decoder Units 36
3.4 Segmented Array DAC 37
3.5 The Proposed DAC Cell 38
Chapter 4 CIRCUIT IMPLEMENTATION 42
4.1 Layout View of the DAC 41
4.2 Simulation Results 45
Chapter 5 Conclusion AND FUTURE WOK 49
Reference 50


LIST OF FIGURES
Chapter 2
Figure 2.1 Illustration of INL, DNL and nonmonotonicity 9
Figure 2.2 Gain error and Offset error 9
Figure 2.3 Classification DAC 14
Figure 2.4 General current divisions DAC 15
Figure 2.5 R-2R ladder circuit 17
Figure 2.6 Off-chip output resistor load 18
Figure 2.7 Current output using a transimpedance 18
Figure 2.8 General voltage divisions DAC 20
Figure 2.9 General charge divisions DAC 22
Figure 2.10 The charge redistribution switched capacitor converter 22

Chapter 3
Figure 3.1 Characterization of real current source 26
Figure 3.2 The conventional current mirror circuit 26
Figure 3.3 The differential current switch pair design 28
Figure 3.4 The proposed spike-free current mirror 29
Figure 3.5 Feedback circuit of the current mirror 30
Figure 3.6 Current mirror accuracy analyzes 31
Figure 3.7 Current mirror accuracy simulation results 32
Figure 3.8 Common-centroid segment cells 35
Figure 3.9 A 10-bit fully segmented current-steering DAC 36
Figure 3.10 Block diagram of the DAC 37
Figure 3.11 Block diagram of the DAC 37
Figure 3.12 The schematic with negative-feedback circuit 39
Figure 3.13 Current Cell Unit 40

Chapter 4
Figure 4.1 Layout photo of the proposed DAC 41
Figure 4.2 Layout views of the segment cells 43
Figure 4.3 Floorplan of segment cells 43
Figure 4.4 Mathematical calculation of random variable 45
Figure 4.5 Code transition of the post layout simulation 46
Figure 4.6 The simulation results of the current mirrors in Fig. 3.2 & Fig. 3.4 47
Figure 4.7 Simulation results of DNL and INL 47

LIST OF TABLES
Table 2.1 Binary, thermometer, 1-of-n codes 7
Table 2.2 Performance of different current division DAC 19
Table 2.3 Performance of DACs 24
Table 3.1 Current mirror circuits characteristics comparison 31
Table 4.1 Post-layout simulation specification 48
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