在現代通訊應用中，類比電路和數位資料的傳輸必須透過一些介面傳輸，而在大家都趨向於SOC的時代中，面積跟功率都成為一個重要的關鍵，而在一般的數位類比轉換器，速度都已經可以達到需求，不過在面積跟功率都還有挑戰的空間，針對這些問題，我們研究出了一種新的電流鏡切換方式，他不但可以顧到面積問題，並且在功率消耗中也可以達到低功率的要求，精準度也都可以達到我們所期望的。
Current-steering DAC的基本概念是利用電流源的方式，藉由選擇電路來使開關導通來將所需的電流切換至輸出，而Binary-weight DAC與其他架構比較起來current steering DAC具有較快的操作速度，但是以電流形式實現必須考慮以下非線性的特性：電流源的不匹配，電流源的有限輸出阻抗和負載電阻之非線性
當解析度越來越高時Binary-weighted DAC的monotonicity與glitch兩項問題將會越來越嚴重；相對地，當segmented DAC的解析度越來越大時，面臨Binary to Thermometer code decoder的複雜度與面積大幅提升，使得設計上越來越困難，且Binary to Thermometer code decoder的功率消耗也將很大。因此我們提出的triple segment DAC可以解決上述的問題，而且藉著這種混合的架構使得高解析度DAC的難度降低了許多。在10位元的轉換器中，10位元完全以segmented DAC來做為一個基本架構，並且使用了一個新型的電流鏡。如此不但節省了面積的浪費並且在功率上面獲得了很大的改進。此外採取外掛電阻的方式直接將輸出訊號由電流轉成電壓。
在電流源的部分共包含有三個部分，分別為參考電流源、負回授增益級與電流鏡輸出級，藉著負回授增益級，大大增加了電流鏡輸出級的阻抗與其和參考電流源間的匹配準確度，並且能夠使電路在負回授的穩定下，能夠準確的使電路快速穩定。因此對於之前討論的電流源不匹配與負載電阻之非線性兩大問題提供有效的解決方法。電流源架構的構想與gain-boosting的觀念類似，藉由負回授的增益級來提高由輸出電晶體所看到的輸出阻抗。
晶片的實現上，利用0.18 um CMOS 製程所研製。整個DAC的模擬，在10MHz時，其INL能收斂在+0.14LSB ~ -0.14LSB之間，DNL能收斂在+0.14LSB ~ -0.13LSB之間，整個DAC的步階響應，能收斂於0.1us以內，也就是能操作於10MHz，整體功率消耗為2.5mW。在晶片的模擬驗證上，證實了此架構的可行性。

A low-power digital-to-analog converter for portable electronics is introduced. A fully segmented architecture with a spike-free current mirror is presented to improve the INL/DNL and reduce the power consumption of the high-speed current steering DAC. The presented 10-bit DAC have been implemented in 0.18um 1P6M CMOS standard technology, and its core area is 0.27mm2. The simulation results show the DNL/INL is 0.14/0.14 at a conversion rate of 10MHz, and consume 2.5mW of power from a 1.8V supply voltage. There is a strong demand to promote the performance of the high-speed digital-to-analog converter (DAC) in many telecommunication systems, such as WLAN, AWG, and HDTV. The full segmented DAC is interested because of their fast operation speed, less consumed area, and high power efficiency. Many efforts have been devoted to improve the resolution and settling time for these current steering DACs. 
The differential switch pair is popular to form the basic current switch in current cell of the segmented DAC. The output voltage of the current cell is hence stabilized while the current branch is cut off. However, a dummy load should be added at the other side of the differential switch to avoid this switch entering cut-off mode. Thus, an additional power would be wasted on this dummy path. Moreover, there are a couple of deglitch circuits are needed to suppressed the spike caused by the abnormal switching on these differential pairs. The extra hardware and their power consumption would be paid.
In this literature, a new high-accuracy current cell with spike-free switching for the full segmented current steering DAC is proposed. The output voltage of the current cell can be kept on a fixed voltage level with no other output path is needed while the current cell is turned off. The power dissipated on the dummy load in the conventional DAC can thus be excluded. Since no deliberated deglitch circuits in the proposed current steering circuit are required, less hardware and power would be achieved for a 10-bit full segmented DAC.

Chapter 1 Introduction                                      1
Chapter 2 The Digital-to-Analog Converters Overview        5
	2.1 Digital Code                                             5
	2.2 Digital-to-Analog Converter Specifications                    7
	2.3 Converter Type                                         13
	2.4 Classification of Digital-to-Analog Converter                 14
		2.4.1 Current division DACs                              15
		2.4.2 Voltage division DACs                              19
		2.4.3 Charge division DACs                               21
2.5 Comparisons of DACs                                    24
Chapter 3 The 10-Bit Current-Steering DAC                 25
	3.1 Current Mirror Analysis                                   25
		3.1.1 Current mirror circuit simulation results and comparisons   31
	3.2 Mismatch Effect                                     33
		3.2.1 Random error                                  33
		3.2.2 Systematic and graded error                       34
	3.3 Partition Current-Steering DAC                            35
       3.3.1Decoder Units                                      36
  3.4 Segmented Array DAC                                  37
	3.5 The Proposed DAC Cell                                 38
Chapter 4 CIRCUIT IMPLEMENTATION                42
	4.1 Layout View of the DAC                                 41
	4.2 Simulation Results                                       45
Chapter 5 Conclusion AND FUTURE WOK                 49
Reference                                                   50


LIST OF FIGURES
Chapter 2
Figure 2.1  Illustration of INL, DNL and nonmonotonicity                        9
Figure 2.2  Gain error and Offset error                                        9
Figure 2.3  Classification DAC                                             14
Figure 2.4  General current divisions DAC                                    15
Figure 2.5  R-2R ladder circuit                                             17
Figure 2.6  Off-chip output resistor load                                      18
Figure 2.7  Current output using a transimpedance                              18
Figure 2.8  General voltage divisions DAC                                   20
Figure 2.9  General charge divisions DAC                                    22
Figure 2.10  The charge redistribution switched capacitor converter               22

Chapter 3
Figure 3.1  Characterization of real current source                              26
Figure 3.2  The conventional current mirror circuit                             26
Figure 3.3  The differential current switch pair design                           28
Figure 3.4  The proposed spike-free current mirror                             29
Figure 3.5  Feedback circuit of the current mirror                              30
Figure 3.6  Current mirror accuracy analyzes                                  31
Figure 3.7  Current mirror accuracy simulation results                           32
Figure 3.8  Common-centroid segment cells                                   35
Figure 3.9  A 10-bit fully segmented current-steering DAC                       36
Figure 3.10  Block diagram of the DAC                                      37
Figure 3.11  Block diagram of the DAC                                      37
Figure 3.12  The schematic with negative-feedback circuit                       39
Figure 3.13  Current Cell Unit                                              40

Chapter 4
Figure 4.1  Layout photo of the proposed DAC                                41
Figure 4.2  Layout views of the segment cells                                 43
Figure 4.3  Floorplan of segment cells                                       43
Figure 4.4  Mathematical calculation of random variable                         45
Figure 4.5  Code transition of the post layout simulation                         46
Figure 4.6  The simulation results of the current mirrors in Fig. 3.2 & Fig. 3.4        47
Figure 4.7  Simulation results of DNL and INL                                47

LIST OF TABLES
Table 2.1  Binary, thermometer, 1-of-n codes                                   7
Table 2.2  Performance of different current division DAC                        19
Table 2.3  Performance of DACs                                           24
Table 3.1  Current mirror circuits characteristics comparison                     31
Table 4.1  Post-layout simulation specification                               48

Reference
[1]. R. Hester, S. Mukherjee, D. Padgett, D. Richardson, W. Bright, M. Sarraj, M. Agah, A. Bellaouai, I. Chaudry, J. Hellums, K. Islam, A. Loloee, J. Nabicht, F. Tsay, and G. Westphal, “CODEC for echocanceling, full-rate ADSL modems,” in ISSCC Dig. Tech. Papers, 1999, pp. 242–243.
[2]. T. Miki, Y. Nakamura, S. Asai, and Y. Akasaka, “An 80-Mhz 8-bit CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 983–988, Dec. 1986.
[3]. Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, “A 10-b 70-MS/s CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 26, pp. 637–642, Apr. 1991.
[4]. G. Van der Plas, J. Vandenbussche, A. van den Bosch, M. Steyaert, W. Sansen, and G. Gielen, “MOS transistor mismatch for high accuracy applications,” Proc. IEEE 1999 ProRISC, pp. 529–533, Nov. 1999.
[5]. H. P. Tuinhout and M.Vertregt, “Test structures for investigation of metal coverage effects on MOSFET matching,” in Proc IEEE 1997 Int. Conf. Microelectronic Test Structures, vol. 10, Mar. 1997, pp. 179–183.
[6]. K. H. Cheng, C. C. Chen, and P. Y. Li, “A high accurate and high output impedance current mirror,” in Proc. WSEAS Conf. CSCC, 2002, pp. 41-43.
[7]. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. 2nd Ed. New York: Oxford, 2002.
[8]. B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.
[9]. D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons, 1996.
[10]. G. A. M. Van Der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert, and G. G. E. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,” IEEE J. Solid-State Circuits, vol. 34, pp. 1708-1718, Dec. 1999.
[11]. E. Sackinger; W. Guggenbuhl, “A high-swing, highimpedance MOS cascode circuit”, IEEE Journal of Solid-State Circuits, Vol.25 1990 pp. 289–298.
[12]. Y. Cong and R. L. Geiger, “Switching-Sequence optimization for gradient error-compensation in thermometer-decoded DAC array,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 585–595, July 2000.
[13]. C. H. Lin and K. Bult, “A 10-b, 500-Msamples/s CMOS DAC in 0.6 mm,” IEEE J. Solid-State Circuits, vol. 33, pp. 1948–1958, Dec. 1998.
[14]. J. Vandenbussche, G. Van der Plas, A. Van den Bosch, W. Daems, G. Gielen, M. S. J. Steyaert, and W. Sansen, “A 14b 150 MSample/s update rate Q2 random walk CMOS DAC,” in ISSCC Dig. Tech. Papers, 1999, pp. 146–147.
[15]. V. D. A. Bosch; M. A. F. Borremans; M. S. J. Steyaert; W. Sansen, “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, Volume: 36 , Issue: 3 , pp, 315 – 324, March 2001
[16]. M. Albiol; J. L. Gonzalez; E. Alarcon, “Improved design methodology for high-speed high-accuracy current steering D/A converters,” Design, IEEE Europe Conference and Exhibition Automation and Test, 2003 , pp, 636 – 641
[17]. J. Vandenbussche; G. Van der Plas; W. Daems; A. Van den Bosch; G. Gielen; M. Steyaert; W. Sansen, “Systematic design of high-accuracy current-steering D/A converter macrocells for integrated VLSI systems,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing , Volume: 48 , Issue: 3 , March 2001 ,pp,300 - 309
[18]. M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement. New York: Oxford, 2001.
[19]. T. Wu, C. Jih, J. Chen, and C. Wu, “A low glitch 10-bit 75-MHz CMOS video D/A converter,” IEEE J. Solid-State Circuits, vol. 30, no. 1, pp. 68–72, Jan. 1995.
[20]. D. Mercer and L. Singer, “12 bit 125 MS/s CMOS D/A designed for spectral performance,” in Proc. Int. Symp. Low Power Electronics and Design, 1996, pp. 243–246.
[21]. J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 12 bit intrinsic accuracy high speed CMOS DAC,” IEEE J. Solid-State Circuits, vol. 33, pp. 1959–1969, Dec. 1998.
[22]. B. Tesch and J. Garcia, “A low glitch 14 bit 100 MHz D/A converter,” IEEE J. Solid-State Circuits, vol. 32, pp. 1465–1469, Sept. 1997.
[23]. J. Bastos, M. Steyaert, and W. Sansen, “A high yield 12-bit 250-MS/s CMOS D/A converter,” in Proc. IEEE 1996 CICC, May 1996, pp. 431–434.
[24]. C-H. Lin and K. Bult, “A 10b 500 MSamples/s CMOS DAC in 0.6 mm2,” IEEE J. Solid-State Circuits, vol. 33, pp. 1948–1958, Dec. 1998.
[25]. K. Lakshmikumar, R. Hadaway, and M. Copeland, “Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057–1066, Dec. 1986.
[26]. Deveugele, J.; VanderPlas, G.; Steyaert, M.; Gielen, G.; Sansen, W., “A Gradient-Error and Edge-Effect Tolerant Switching Scheme for a High-Accuracy DAC,” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, vol. 51, pp. 191–195, Jan 2004
[27]. H. H. Bae; J. S. Yoon; M. J. Lee; E. S. Shin; S. H. Lee, “A 3 V 12b 100 MS/s CMOS D/A converter for high-speed system applications,” ISCAS '03, Vol.1, May 2003, pp.I-869 - I-872
[28]. J. Hyde; T. Humes; C. Diorio; M. Thomas; M. Figueroa,”A 300-MS/s 14-bit digital-to-analog converter in logic CMOS,” IEEE J. Solid-State Circuits, , Vol.38, May 2003, pp.734-740
[29]. K. Khanoyan; F. Behbahani; A. A. Abidi, “A 10 b, 400 MS/s glitch-free CMOS D/A converter,” IEEE International Symposium on VLSI Circuits, 1999. Digest of Technical Papers., June 1999, pp.73-76
[30]. C. Ionascu; D. Burdia, ” Design and implementation of video DAC in 0.13/spl mu/m CMOS technology,” IEEE International Signals, Circuits and Systems, Vol.2, July 2003, pp.381-384
[31]. A. Van den Bosch; M. Borremans; J. Vandenbussche; G. Van der Plas; A. Marques, J. Bastos; M. Steyaert; G. Gielen; W.Sansen, ”A 12 bit 200 MHz low glitch CMOS D/A converter,” IEEE International Custom Integrated Circuits Conference, May 1998, pp. 249-252
[32]. M. R. Hassanzadeh,; J. Talebzadeh,; O. Shoaei, ”A high-speed, current-steering digital-to-analog converter in 0.6-/spl mu/m CMOS,” IEEE International Conference on Electronics, Circuits and Systems, Vol.1, Sept. 2002, pp.9-12
[33]. Y. Yongsang; S. Minkyu, “Design of a 1.8V 10bit 300MSPS CMOS digital-to-analog converter with a novel deglitching circuit and inverse thermometer decoder,” IEEE International Asia-Pacific Conference on Circuits and Systems, Vol.2, Oct. 2002, pp.311-314
[34]. D. Mercer, ”A 16-b D/A converter with increased spurious free dynamic range,” IEEE J. Solid-State Circuits, Vol.29, Oct. 1994, pp.1180-1185
[35]. S. Y. Chin; C. Y. Wu, ”A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources,” IEEE J. Solid-State Circuits, Vol.29, Nov. 1994, pp.1374-1380
[36]. D. Mercer; L. Singer, “12-b 125 MSPS CMOS D/A designed for spectral performance,” IEEE International Symposium on Low Power Electronics and Design, Aug. 1996, pp.243 -246
[37]. Z. Yijun; Y. Jiren, ”An 8-bit 100-MHz CMOS linear interpolation DAC,” IEEE J. Solid-State Circuits, Vol.38, Oct. 2003, pp.1758-1761
[38]. A. R. Bugeja; B. S. Song; P. L. Rakers; S. F. Gillig, “A 14-b, 100-MS/s CMOS DAC designed for spectral performance,” IEEE J. Solid-State Circuits, Vol.34, Dec. 1999, pp.1719-1732
[39]. A. R. Bugeja; B. S. Song, “A self-trimming 14-b 100-MS/s CMOS DAC,” IEEE J. Solid-State Circuits, Vol.35, Dec. 2000, pp. 1841-1852
[40]. M. P. Tiilikainen, ”A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC,” IEEE J. Solid-State Circuits, Vol.36, July 2001, pp.1144-1147
[41]. J. Hyde; T. Humes; C. Diorio; M. Thomas; M. Figueroa, “A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25 /spl mu/m CMOS,” IEEE International Symposium on VLSI Circuits Digest of Technical, June 2002, pp.328-331

[42]. A. Zeki; H. Kuntman, “Accurate and high output impedance current mirror suitable for CMOS current output stages”, Electronics Letters, Vol.33, 1997, pp.1042–1043.
[43]. K. H. Cheng; C. C. Chen; C. F. Chung, “Accurate current mirror with high output impedance,” The 8th IEEE International Conference on Electronics, Circuits and Systems, Vol.2, 2001, pp.565–568.
[44]. N. U. Andersson; J. J. Wikner, “A strategy for implementing dynamic element matching in current-steering DACs,” IEEE Southwest Symposium on Mixed-Signal Design, Feb. 2000, pp. 51-56
[45]. K. H. Cheng; C. C. Chen; P. Y. Li, “A high accurate current mirror with high output impedance,” in Proc. WSEAS Conf. CSCC, 2002, pp.41-43