隨著測試資料不斷成長，測試成本也日益增加。為了降低測試成本，針對多重鏈結串列的測試架構下，本篇論文提出一個適用於大型電路的壓縮方式。此方法對於矽智財(Intellectual Property, IP)模組，或是單晶片系(System-On-a-Chip, SoC)都非常適用。同時考量在低成本的測試設備環境中，盡可能地降低電能轉換以及增加壓縮率。

  此壓縮架構基礎為固定長度的電能轉換紀錄方式，當測試資料的電能轉換頻率較低時，我們使用一個過濾器過濾不必要資料轉換，並保留目前的電能狀態，以降低電量的耗損。我們也提出一個新的演算法，可以重新配置多重鏈結串列結構，使其電能耗損率更低，壓縮結果更好。除此之外，本篇論文亦提出一個新的矩陣轉換方式，可以找出隱藏的資料相依關係。結果顯示本論文提出的方法，可同時降低電能轉換以及測試資料量。

  實驗結果顯示，當超大型積體電路的複雜度越益成長，測試所需的輸入腳位增加幅度卻非常低。針對ISCAS’89測試電路，使用MinTest或TetraMAX產生的測試資料，本論文提出的方法，平均壓縮率為63%。比對Selective Scan Slice (SSS)方法，對於MinTest測試資料，瞬間最大轉換電能減少3倍，平均電能轉換減少6.6倍；對於TetraMAX測試資料，瞬間最大電能轉換減少2.3倍，平均電能轉換減少5.6倍。平均硬體增加幅度為MinTest的6%及TetraMAX的6.5%。

As test data volumes continue to grow, test costs also increase. To lower test costs, this paper presents a new compression method for testing large circuits, based on multiple scan-chains and an unknown structure. This method is targeted at intellectual property (IP) cores and system-on-a-chip (SoC) circuits. This study considers the shift-in power and compression ratio in low-cost ATE environments. 

  This study presents a new compression architecture with fixed length for testing large circuits. Because power-aware test data are not changed frequently, a selector is used to filter the unnecessary status, and buffers are used to hold the back data. A new algorithm is proposed to assign multiple scan-chains. An improved linear dependency compute method is also proposed to determine the hidden dependency between scan-chains. Experimental results show that the proposed method can reduce both test data volume and shift-in power. 

  The results showed that when the VLSI circuit grows in complexity, number of input pins required for testing increases slowly. The average compression ratio of the proposed method was 63% for MinTest and TetraMAX. On ISCASce for both tests, a value of 3x/6.6x was observed for MinTest and 2.3x/5.6x for TetraMAX, after comparing Selective Scan Slice (SSS) with the proposed method. The averages of hardware overhead costs were 6% for MinTest and 6.5% for TetraMAX.

TABLE OF CONTENTS

	
中文摘要………………………………………………………………..	I
英文摘要...……………………………………………………………...	III
Table of Contents ……………………………………………...	V

List of Figures ………………………………………………...	IX

List of Tables ………………………………………………….	XV
	
	
	
Chapter 1 INTRODUCTION ………………………………	1
	
1.1 Motivation ……………………………………………………………………..	3
1.2 Thesis Overview ……………………………………………………………...	5
	
Chapter 2 BASIC CONCEPTS ……………………………	6
	
2.1 Faults ……………………………………………………………………………	6
     2.1.1 Circuit Defects and Faults ………………………………………………	7
     2.1.2 Fault Detection ………………………………………………………….	10
2.2 Fault Simulation …………………………………………………….	13
2.3 Full-Scan Architecture …………………….………………………..	15
2.4 Built-In Self Test …………………………………………………….	18
    2.4.1 BIST Pattern Generation ……………………………………………........	19
    2.4.2 Test Pattern Generation for BIST ……………………………………….	20
    2.4.3 Seed Calculation of Linear Feedback Shift Register ……………………	24
    2.4.4 Test-Per-Clock BIST Systems …………………………………………..	25
    2.4.5 Test-Per-Scan BIST Systems ……………………………………………	27
    2.4.6 Transformed Patterns For BIST …………………………………………	29
    2.4.7 Circuit Partitioning for BIST ……………………………………………	33
    2.4.8 Built-In Reseeding For BIST …………………………………………….	35
2.5 Low Power Testing ………………………………………………………...	36
    2.5.1 Power Dissipation and Power Issues ……………………………………	36
    2.5.2 The Challenges of Low Power Testing ………………………………….	41
    2.5.3 Low Power Testing Techniques ………………...……………………....	42
        2.5.3.1 DFT-based ………………………………………………………	43
        2.5.3.2 DFT-based ………………………………………………………	45
2.6 Data compression issues …………………..………...………………	47
    2.6.1 Filling unspecified bits ………………………………………………….	50
    2.6.2 Change entropy of the original test data …………………………………	51
    2.6.3 Scan chain reordering …………………………………………………….	51
	
Chapter 3 PREVIOUS METHODOLOGIES …………….	52
	
3.1 Modifying-Bit Architecture …………………………………………	52
3.2 Multiple Polynomial LFSR Architecture …………………………..	55
3.3 Test Data Compression Methods …………………………………..	56
    3.3.1 Single scan chain …………………………………………………………	56
        3.3.1.1 Run-Length code and Golomb code …………………………….	56
        3.3.1.2 FDR code and VIHC code ……………………………………….	56
        3.3.1.3 EFDR code ……………………………………………………….	57
        3.3.1.4 Alternating RL code and RL-Huffman code ……………………	58
        3.3.1.5 Block merging technique ……………………………………….	58
    3.3.2 Multiple scan chain ………………………………….………………….	61
        3.3.2.1 Selective scan slice encoding …………………………………...	61
        3.3.2.2 Dictionaries with selective entries and fixed-length indices……	65
        3.3.2.3 Hybrid test data compression method ……………………….....	68
        3.3.2.4 Three-stage compression approach ……………………………..	71
        3.3.2.5 Multilayer data copy scheme …………………………………….	75
	
Chapter 4 PROPOSED HARDWARE ARCHITECTURE .....	78
	
4.1 Decompression Architecture ……………………………………….....	78
4.2 Detail of n to m Decompressor ……………………………...………	80
4.3 Dictionary based …………………………………………………….	80
4.4 Run-Length based …………………………………………………..	81
	
Chapter 5 PROPOSED COMPRESSION ALGORITHMS	84
	
5.1 Multiple Scan-Chain Reconstruction ……………………………....	85
5.2 Centralized-Filling ………………………………………………….	91
5.3 Linear Dependency computes ……………………………………...	92
5.4 Test Slices Difference ……………………………………………….	94
5.5 Symbol decreases …………………………………………………...	94
5.6 Encoding …………………………………………………………….	100
	
Chapter 6 PROPOSED PSEUDO CYCLE ………………	101
	
6.1 Overview Of Architecture …………………………………………..	101
6.2 Detail Of Dcompressor Architecture …………………………….....	105
6.3 Proposed compressing algorithm …………………………………..	111
    6.3.1 Slice the original pattern …………………………………………………	112
    6.3.2 Getting solving vector ……………………………………………………	113
    6.3.3 Getting ATE data …………………………………………………………	117
	
	
	
Chapter 7 SIMULATION RESULTS …………………….	124
	
7.1 Results without scan-chains reconstruction …………………...........	126
7.2 Results with scan-chains reconstruction …………………………....	135
7.3 Pseudo cycle ………………………….….………………………….	142
	
Chapter 8 CONCLUSIONS ………………………………...	145
8.1 Contributions ………………………………………………………	145
8.2 Disadvantages ………………………………………………………	147
	
References ……………………………………………………..	148
	
Appendix ………………………………………………………	162
Appendix 1 MaxClique.cpp ……………………………………………..	162
Appendix 2 SSS.cpp …………………………………………………….	169
Appendix 3 Huffman.cpp …………………………………………….....	174
Appendix 4 MutiCode.cpp ……………………………………………...	178



 

LIST OF FIGURES



Figure 1.1     Testing of embedded cores…...……………………………..……	2
Figure 1.2     Architecture of the BIST ………………………………………...	2
Figure 1.3     Principle of testing ………………………………………………	3
	
Figure 2.1     A circuit of fault-free and faulty ………………………………...	8
Figure 2.2     An example of single stuck-at fault model ………………………	8
Figure 2.3    A three-input NAND gate with, (a) no faults (b) x1 with ans-a-0 fault, and (c) x1 with an s-a-1 fault …………………………….	9
Figure 2.4     An example of a single stuck-at fault ……………………………	11
Figure 2.5     A test for x1 s-a-0 detects a different between the faulty circuit and the fault-free circuit ………………………………………..	12
Figure 2.6     Calculated the fault coverage ……………………………………	13
Figure 2.7     Difficulty of detecting stuck-at-faults in a sequential circuit ……	16
Figure 2.8     Example of scan chain (a) A muxed-D scan cell (b) A sample scan chain ………………………………………………………	16
Figure 2.9    Conventional full-scan designed circuit …………………………	17
Figure 2.10    Exhaustive pattern generator ……………………………………	21
Figure 2.11    Backtracing for pseudo-exhaustive testing ………………………	22
Figure 2.12    Standard linear feedback shift register ………………………….	23
Figure 2.13    A 4-stage LFSR connected to a chain …………………………...	24
Figure 2.14    The remaining equations of the scan flip-flops ………………….	25
Figure 2.15    The matrix which represents the equations ……………………...	25
Figure 2.16    Test-Per-Clock scheme (a) Test-per-clock (b) Large input count test-per-clock system ………………………………………….	26
Figure 2.17    Test-Per-Scan scheme (a) Simple (b) Alternative system ………	27
Figure 2.18    STUMPS test-per-scan testing system ………………………….	28
Figure 2.19    Example of a Rectangle in the B-Matrix and its Corresponding Bit-Fixing Logic ………………………………………………	30
Figure 2.20    Cube Mapping with Source Cube a1'a2' (0,1,X) and Image cube a2'a3 (X,0,1)……………………………………………………	31
Figure 2.21    Block Diagram for Generating Transformed Patterns …………...	32
Figure 2.22    Output cones ……………………………………..………………	33
Figure 2.23    General and independent of the underlying BIST scheme ………	34
Figure 2.24    A 4-stage LFSR with Reseeding circuit …………………………	36
Figure 2.25    Dynamic power dissipation in a CMOS logic gate………………	37
Figure 2.26    Illustration of manufacturing yield loss …………………………	39
Figure 2.27    Example of weighted transition count …………………………	40
	
Figure 3.1     The architecture of modifying-bit ………………………………	53
Figure 3.2     Obtaining the useful pattern ………………………...……………	54
Figure 3.3     Multiple Polynomial LFSR Architecture ……………...…………	55
Figure 3.4     Example of various schemes (a) initial test vector (b) Run-Length code. (c) Golomb code (d) FDR code (e) VIHC code (f) EFDR code (g) Alternating RL code (h) RL-Huffman code …………..	57
Figure 3.5     Example of block merging technique …………...……………….	60
Figure 3.6     The decompression architecture of selective scan slice encoding ……………...………………………...………………	62
Figure 3.7     Example of selective scan slice encoding (a) initial test set (b) X-filling ……………...………………………...……………….	63
Figure 3.8     Encoding of figure 3.7…………………………………….………	64
Figure 3.9     The decompression architecture of dictionary-based compression scheme ……………...………………………...………………...	66
Figure 3.10    Example of grouping the scan chains into several clique ………..	67
Figure 3.11    Overall framework of hybrid test data compression method …….	68
Figure 3.12    Example of scan chain compaction (a) single scan chain and initial test set (b) conflict graph for scan cells (c) compacted scan chain network …………………………………………….	69
Figure 3.13    The decompression architecture of hybrid test data compression method …………………………………………………………	70
Figure 3.14    The encoding procedure of three-stage compression approach …	71
Figure 3.15    The decompression architecture of three-stage compression approach ………………………………………………………..	72
Figure 3.16    Example of width compression (a) initial test set (b) conflict graph for scan chains (c) compressed test data and the fan-out structure (d) compressed test data and the gated fan-out structure ………………………………………………………	73
Figure 3.17    Figure 3.17 Example of width compression after figure 3.16 (a) compressed test data and the fan-out structure (b) compressed test data and the gated fan-out structure ………………………	74
Figure 3.18    Illustration of the decoding architecture (a) decoding architecture (b) switching box (c) switching box implementation (d) multilayer organization ………………………………………..	76
Figure 3.19    Example of multilayer data copy scheme ……………………….	77
	
Figure 4.1    Decompression architecture (a) overview of test environment. (b) detail of decompressor …………………………………………	79
Figure 4.2    Decompressor architecture of method 2 …………………………	81
Figure 4.3    Relationship of M2 between codeword length and average compression ratio (b) average symbol ratio ……………………	83
	
Figure 5.1    Main steps of the proposed procedure …………………………..	84
Figure 5.2    Example of conflicts in group (a) initial test cube (b) conflict in grouping (c) conflict checking …………………………………	86
Figure 5.3    Pseudo-code of conflict checking ………………………………..	87
Figure 5.4    Pseudo-code of multiple scan-chain assignment ………………...	88
Figure 5.5    Example of scan-chain reconstruction (a) initial test cubes (b) TSG and corresponding pre-group after sorting by X (c) component of scan-chains (d) test slices data and corresponding pre-scan ………………………………………………………..	90
Figure 5.6    Centralized filling and linear dependency computes ……………	91
Figure 5.7    Example of trasnsitional Gauss-Jordan Elimination (a)initial test set (b) general (c) transform into transition matrix (d) result ……………………………………………………………	93
Figure 5.8    Compression processes after figure 5.6 (a) test slices difference (b) decreased symbol and read enable data ……………………	95
Figure 5.9    Pseudo-code of Symbol decreases ………………………………	97
Figure 5.10   Example of reconvert logic feedback error (a) dependency matrix and corresponding reconvert logic (b) reconvert tree of v1~v4 (c) after reconvert logic feedback checking ……………………	99
Figure 5.11   Encoded data volume in figure 5.8 (a) encoded data and statistics of distance between 1s (b) M1: Dictionary based (c) M2: Run-Length based ……………………………………………...	100
	
Figure 6.1    Overview of test environment ……………………………………	102
Figure 6.2    Detail of decompressor architecture ……………………………..	104
Figure 6.3    A sample of PPRPG linked to Selection ………………………….	106
Figure 6.4    A sample of PPRPG linked to Selection Mux ………………….	108
Figure 6.5    Set the decompressor in mode 0 …………………………………	109
Figure 6.6    Set the decompressor in mode 1 …………………………………	109
Figure 6.7    Mode 1 uses mask. If the bit of mask is 1, we pass it. If the bit of mask is 0, we set the bit in 0 …………………………………..	110
Figure 6.8    Procedure of getting ATE data ………………………………….	111
Figure 6.9    A sample of slicing original patterns ……………………………	113
Figure 6.10   Example of getting solving vector from Vector Set (a) Getting desired Selection from Vector Set (b) Getting MUX of Selection from desired Selection (c) Getting solving Selection from desired Selection (d) Getting solving vector from solving Selection and MUX of Selection ………………………………	115
Figure 6.11   (a) PPRPG architecture (b) the data after 3 cycles (c) simplification data of (b) ………………………………………	118
Figure 6.12   Example of PPRPG data ………………………………………….	119
	
Figure 6.13   Our Architecture Example of getting ATE data (a) solving vector (b) select specific bits (c) the equations of specific bits (d) the seed (e) substitute (d) to (c) will get the matrix (f) solving by Gauss-Elimination and get the ATE data ………………………	122
Figure 6.14   An example of mode 1, we insert these data in Figure 4.5(c) cycle1 ………………………………………………………….	123
	
Figure 7.1    Pseudo-code of implemented SSS ……………………………….	125
Figure 7.2    #SC Curves without scan-chains reconstruction by method 2 (a) TetraMAX (b) MinTest ………………………………………..	133
Figure 7.3    #SC Curves with scan-chains reconstruction by method 2 (a) TetraMAX (b) MinTest ………………………………………..	137
	
 

LIST OF TABLES



Table 2.1     The system of test-per-clock is different from system of the test-per-scan ……………………………………………………..	29
	
Table 3.1     The encoding rules for block merging technique ………………...	62
Table 3.2     Block size encoding for block merging technique ………………..	64
	
Table 4.1     Encoded data and represented interval range …………………….	85
	
Table 7.1     Statistics of ISCAS 89 benchmark ………………………………..	127
Table 7.2     Test Pattern Information of ISCAS’89 benchmark ………………	128
Table 7.3     Data volume comparison results without scan-chains reconstruction by using TetraMAX ……………………………	127
Table 7.4     Data volume comparison results without scan-chains reconstruction by using MinTest and other test set ……………	128
Table 7.5     Hardware of compression results without scan-chains reconstruction …………………………………………………	130
Table 7.6     Test data of compression results without scan-chains reconstruction …………………………………………………	131
Table 7.7     Power comparison results without scan-chains reconstruction …	134
Table 7.8     Data volume comparison results with scan-chains reconstruction .	135
Table 7.9     Data volume comparison results with scan-chains reconstruction by using MinTest and other test set ……………………………	136
Table 7.10    Hardware of compression results with scan-chains reconstruction	139
Table 7.11    Test data of compression results with scan-chains reconstruction .	140
Table 7.12    Power comparison results with scan-chains reconstruction ………	141
Table 7.13    The comparing results with other methods ……………………….	143
Table 7.14    Data volume comparison results by using MinTest and other test set ………………………………………………………………	144

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