隨著可攜式電子產品市場的快速成長，以及人們對於產品輕薄短小和電池的長時效性要求，發展低電流、低功耗的積體電路技術有愈來愈急迫的需要。然而，若藉由供應電壓的下降，雖可有效地節省數位電路的消耗功率，但反而會增加高解析度類比電路設計的困難。因此，如何同時將類比至數位轉換器(Analog-to-Digital Converter)的消耗功率大幅減少，並維持效能不變，這對於混合信號電路的設計者來說是一項很大的挑戰。
由於三角積分調變器(Delta-Sigma Modulator)具有較佳的線性度以及對電路元件變異較不敏感，非常適合用來實現高解析度、高精確度的類比數位轉換器，也因此在音頻及通訊領域有相當多的應用。然而，傳統的三角積分調變器多半需要使用到運算放大器，加上若要使調變器能有足夠好的效能，對系統架構的要求往往在二階以上。雖然雙取樣(Double Sampling)技術可減少運算放大器的使用並降低對運算放大器規格上的要求，同時卻也因為雙取樣電路的關係，對於電路元件的需求增加了一倍。也就是說，雖然省去了運算放大器的功率消耗，但其他電路元件的功率消耗卻增加了。因此，對於傳統二階以上架構或是雙取樣的電路實現方式，較大的消耗功率都是在所難免。
近年的文獻中，新近發展出來的電荷傳輸放大器(Charge-Transfer Amplifier, CTA)技術，最大特點在於其幾近為零的靜態功率消耗。因此，電荷傳輸放大器將能更有效地大幅降低電路之消耗功率。若要發展低功耗的積體電路，利用電荷此技術來實現將會是一可行的辦法。本論文提出不使用運算放大器來實現三角積分調變器的全新技術，並藉由成功發展出全差動式電荷傳輸放大器(FDCTA)以及全差動式電荷傳輸積分器(FDCTI)，實現了此構想。當頻寬為4 kHz，取樣頻率為2.5 MHz時，此調變器之訊號雜訊比(SNR)可達67 dB，解析度達11 bits。當供應電壓為1.8 V時，類比部份的功耗為3.4 μW，總功耗為36 μW。

With rapid growth of the market in the portable electronic products, there is a strong demand for developing less current and low power consumption circuit technique to increase the system level integration density and prolong the battery lifetime. However, the reduced supply voltage results in the power saving in digital circuits, but complicates the design of high resolution analog circuits. It is also a great challenge to maintain the desired performance of the analog-to-digital converters (ADCs) while the power consumption is greatly reduced.
Since delta-sigma (ΔΣ) modulators have better linearity and insensitivity to device variation, they are well suitable for the realization of high-resolution and high-accuracy A/D converters in audio and communications applications. However, it is usually required to design a high-order ΔΣ modulator with the power-hungry opamps to satisfy the specific performance. In some state-of-the-art literatures, double-sampling technique is often used to reduce the performance requirement of opamp at the cost of double devices. In other words, double-sampling technique reduces the power consumed by opamp, but increases that from additional double devices. Consequently, it is difficult to reduce the power consumption of the ΔΣ modulators with conventional architecture and technique.
From the recent literatures, we know that the advantage of the charge-transfer amplifier (CTA) technique is the almost zero static power consumption. Therefore, the CTA technique exhibits a substantial power-saving feature and it will be an attractive method for low-power application. This research proposes a brand-new technique without the use of opamp to realize the delta-sigma (ΔΣ) modulator by developing both the fully-differential charge-transfer amplifier (FDCTA) and integrator (FDCTI). The presented ΔΣ modulator reaches a 67 dB of peak SNR when the bandwidth is 4 kHz, and the sampling rate is 2.5 MHz. The power consumption of the analog part of this modulator is 3.4 μW, and the total power consumption of the whole modulator is 36 μW at a 1.8 V of supply voltage.

Table of Contents

CHAPTER 1	INTRODUCTION	1
1.1	Motivation	1
1.2	Organization	2
CHAPTER 2	FUNDAMENTALS OF DS MODULATOR	3
2.1	Introduction	3
2.2	Performance Metrics	4
2.2.1	Resolution	4
2.2.2	Signal-to-Noise Ratio (SNR)	5
2.2.3	Signal-to-Noise plus Distortion Ratio (SNDR)	5
2.2.4	Dynamic Range (DR)	5
2.3	Quantization	6
2.3.1	Mid-tread Quantization	6
2.3.2	Mid-rise Quantization	7
2.3.3	Quantization Error	8
2.3.4	Single-bit Quantization	11
2.3.5	Multi-bit Quantization	12
2.4	Oversampling Technique	13
2.5	Noise Shaped DS Modulator	15
2.5.1	First-Order Noise-Shaping	16
2.5.2	Second-Order Noise-Shaping	119
2.5.3	Higher Order Noise Shaping	22
2.5.4	Single-Loop Topology	23
2.5.5	Cascade Topology	24
2.6	Multibit Quantization	25
2.6.1	Switch Capacitor Summing	26
2.6.2	Summer Opamp	26
CHAPTER 3	THE DESIGN OF CHARGE-TRANSFER AMPLIFIER FOR DS MODULATOR	28
3.1	Introduction	28
3.2	Conventional Charge-Transfer Amplifier (CTA)	28
3.3	Nonidealities of Charge-Transfer Amplifier	30
3.3.1	Threshold Voltage Effect	30
3.3.2	Residual Precharge Current (PRC)	31
3.3.3	Input Signal Polarity Problem	31
3.4	Improvement of Charge-Transfer Amplifier	31
3.4.1	CMOS Charge-Transfer Amplifier (CMOS CTA)	32
3.4.2	Differential Charge-transfer Amplifier (DCTA)	33
3.5	Fully-Differential Charge-Transfer Amplifier (FDCTA)	36
3.5.1	Topology of Fully-Differential Charge-Transfer Amplifier	36
3.5.2	Clock arrangement	38
3.5.3	Simulation Results	38
3.6	Fully-Differential Charge-Transfer Integrator (FDCTI)	39
3.6.1	Charge-Transfer Integrator (CTI)	40
3.6.2	Topology of Fully-Differential Charge-Transfer Integrator	41
3.6.3	Simulation Results	42
CHAPTER 4	A ULTRA LOW-POWER SECOND-ORDER DS MODULATOR	44
4.1	Introduction	44
4.2	System Level Consideration	44
4.2.1	Architecture	45
4.2.2	System Simulation	45
4.3	Circuit Implementation	47
4.3.1	Ultra Low-Power Comparator	47
4.3.2	Nonoverlapped Clock Generator	49
4.3.3	CTA-Based Second-Order 
4.4	Simulation Results	53
4.5	Experimental Results	55
4.5.1	Input Termination Circuit	57
4.5.2	Regulator Circuit	58
4.5.3	Reference Voltage Generator	59
4.5.4	Filter Tank	59
4.5.5	Layout and Pin Assignment	60
4.5.6	Measurement Results	61
4.6	Summary	64
CHAPTER 5	CONCLUSIONS	66
5.1	Conclusions	66
5.2	Future Works	67
REFERENCE	68


List of Figures

Chapter 2
Figure 2.1 Block diagram of the conventional A/D converter	3
Figure 2.2 Block diagram of the oversampling A/D converter	4
Figure 2.3 SDR/SNDR versus input power of an A/D converter	6
Figure 2.4 Characteristic of mid-tread quantization	7
Figure 2.5 Characteristic of mid-rise quantization	8
Figure 2.6 The linear model of quantization error	8
Figure 2.7 The probability density function of the quantization error	9
Figure 2.8 The power spectral density of the quantization error	10
Figure 2.9 Single-bit quantization and quantization error	11
Figure 2.10 Hysteresis and offset of single-bit quantization	12
Figure 2.11 The comparison of the ideal transfer curve and the practical transfer curve for multi-bit quantization	13
Figure 2.12 The oversampling system without noise shaping	14
Figure 2.13 Quantization noise power spectral density after the lowpass filter	14
Figure 2.14 (a) The architecture and (b) the linear model of aΔΣ modulator ...................... 15
Figure 2.15 The linear model of a first-order ΔΣ modulator................................................. 17
Figure 2.16 The PSD of a first-order ΔΣ modulator.............................................................. 18
Figure 2.17 The linear model of a second-order ΔΣ modulator ............................................ 20
Figure 2.18 The PSD of a noise-shaped ΔΣ modulator ......................................................... 21
Figure 2.19 The performance prediction for OSR and Lth-order modulators....................... 23
Figure 2.20 The single-loop ΔΣ modulator ........................................................................... 24
Figure 2.21 The cascade architecture of ΔΣ modulator......................................................... 25
Figure 2.22 Switch capacitor summing ................................................................................. 26
Figure 2.23 Summer opamp .................................................................................................. 27
Chapter 3
Figure 3.1 (a) The charge-transfer amplifier and (b) the corresponding clocks.................... 29
Figure 3.2 The CMOS charge-transfer amplifier ................................................................ 32
Figure 3.3 The simulation results of COMS CTA with .............................................................
(a) positive polarity input and (b) negative polarity input.................................. 33
Figure 3.4 The differential charge-transfer amplifier (DCTA).............................................. 34
Figure 3.5 The operation of DCTA........................................................................................ 35
Figure 3.6 The simulation results of DCTA .......................................................................... 36
Figure 3.7 The fully-differential charge-transfer amplifier (FDCTA)................................... 37
Figure 3.8 The nonoverlapped clocks.................................................................................... 38
Figure 3.9 The simulation results of FDCTA........................................................................ 39
Figure 3.10 The output offset of FDCTA.............................................................................. 39
Figure 3.11 The charge-transfer integrator (CTI).................................................................. 40
Figure 3.12 The fully-differential charge-transfer integrator (FDCTI) ................................. 41
Figure 3.13 The simulation results of FDCTI ....................................................................... 42
Figure 3.14 The output offset of FDCTI ............................................................................... 43
Figure 3.15 The current of FDCTI ........................................................................................ 43
Chapter 4
Figure 4.1 The block diagram of the CIFB second-order ΔΣ modulator .............................. 45
Figure 4.2 The system simulation model of the proposed ΔΣ modulator.............................. 46
Figure 4.3 The outputs of each integrators ............................................................................ 46
Figure 4.4 The output power spectrum of the proposed ΔΣ modulator................................. 47
Figure 4.5 (a) The ultra low-power comparator and (b) SR latch ......................................... 48
Figure 4.6 The hysteresis and current of ultra low-power comparator ................................. 49
Figure 4.7 The nonoverlapped clock generator ..................................................................... 50
Figure 4.8 The CTA-based second-orderΔΣ modulator and the corresponding clocks ........ 52
Figure 4.9 The outputs of each FDCTI and FDCTA............................................................. 53
Figure 4.10 The offset of each FDCTI and FDCTA.............................................................. 54
Figure 4.11 The output power spectrum of the proposed ΔΣ modulator............................... 54
Figure 4.12 The SNR versus input power ............................................................................. 54
Figure 4.13 The chip layout of the proposed ΔΣ modulator.................................................. 55
Figure 4.14 The setup of experimental environment............................................................. 56
Figure 4.15 The input termination circuit.............................................................................. 57
Figure 4.16 The AC response of the AC coupled lowpass filter ........................................... 58
Figure 4.17 The regulator circuit........................................................................................... 58
Figure 4.18 The reference voltage generator circuit.............................................................. 59
Figure 4.19 The filter tank..................................................................................................... 60
Figure 4.20 The die photograph of the proposed ΔΣ modulator ........................................... 60
Figure 4.21 The pin configuration and pin assignment of the chip....................................... 61
Figure 4.22 The photograph of the experimental DUT board ............................................... 62
Figure 4.23 The measured digital output of DUT ................................................................. 62
Figure 4.24 The measured output power spectrum of DUT.................................................. 63
Figure 4.25 The measured SNR versus input power ............................................................. 63

List of Tables
Chapter 4
Table 4.1 The performance summary of the proposed .......................................................... 55
Table 4.2 The measured performance summary of the proposed ΔΣ modulator................... 64
Table 4.3 The performance comparison ................................................................................ 65

[1]	C. H. Kuo, The Design and Implementation of Low Voltage CMOS Delta Sigma Modulators, Tappei, 1993.
[2]	R. Schreier, and G. C. Temes, Understanding Delta-Sigma Data Converters. IEEE Press Wiley Interscience 2005.
[3]	J. Silva, U. K. Moon, J. Steensgaard, and G. C. Temes, “Wideband Low-Distortion Delta Sigma ADC Topology, ”Electron. Lett., vol. 37, Jun. 2001, pp. 737-738.
[4]	W. J. Marble and D. T. Comer, “Analysis of the dynamic behavior of a charge-transfer amplifier,” IEEE Trans. on Circuits and Systems, vol. 48, Jul. 2001, pp. 793–804.
[5]	W. J. Marble, K. Kotani, and C. S. Petrie, “Practical charge-transfer amplifier design architectures for low-power flash A/D converters,” IEEE Trans. on Circuits and Systems, vol. 51, Nov. 2004, pp. 2157-2164.
[6]	K. Kotani, T. Shbata, and T. Ohmi, “CMOS Charge-Transfer Preamplifier for Offset-Fluctuation Cancellation in Low-Power, High-Accuracy Comparators,” Symp. on VLSI Circuits Digest of Technical Papers, Kyoto, Jun. 12-14 1997, pp. 21-22.
[7]	K. Kotani, T. Shibata, and T. Ohmi, “CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters,” IEEE J. Solid-State Circuits, vol. 33, May 1998, pp. 762-769.
[8]	W. J. Marble and D. T. Comer, “Ultra low power A/D converters using an enhanced differential charge-transfer amplifier,” IEEE Proc. of 26th Conf. on Solid-State Circuits European, , Sweden, Sep. 19-21, 2000, pp. 216-219.
[9]	I. Seo and R. M. Fox, “Low-power switched-capacitor filters using charge-transfer integrators,” IEEE Int. Symp. on Circuits and Systems, Bangkok, May 25-28, 2003, pp. I-609 - I-612.
[10]	M. Ranjbar, G. R. Lahiji, and O. Oliaei, “A low power third order delta-sigma modulator for digital audio applications,” IEEE Int. Symp. on Circuits and Systems, Greece, May 21-24, 2006, pp.4759-4762.
[11]	M. Safi-Harb and G. W. Roberts, “Low power delta-sigma modulator for ADSL applications in a low-voltage CMOS technology,” IEEE Trans. on Circuits and Systems, vol. 52, Oct. 2005, pp. 2075-2089.
[12]	W. J. Marble, K. Kotani, and C. S. Petrie, “Practical charge-transfer amplifier design architectures for low-power flash A/D converters,” IEEE Trans. on Circuits and Systems, vol. 51, Nov. 2004, pp. 2157-2164.
[13]	S. Rabii, and B. A. Wooly, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Kluwer Academic Publishers, 1999.
[14]	National Semiconductor, LM117/LM317A/LM317 3-Terminal Adjustable Regulator Data Sheet, National Semiconductor, Inc., 1997.
[15]	J. Sauerbrey, T. Tille, D. Schmitt-Landsiedel, R. Thewes, “A 0.7-V MOSFET-Only Switched-Opamp 
[16]	A. Q. Safarian, H. A. Aslanzadeh, S. Mehrmanesh, and M. B. Vahidfar, “An enhanced dynamic range low-power delta-sigma modulator for portable voice band applications,” Southwest Symposium on Mixed-Signal Design 2003, Las Vegas, Feb. 23-25, 2003, pp. 263-268.
[17]	D. McDonagh, O. Eljamaly, A. J. Burdett, “lV l4uW Switched-OpampΔΣ-ADC for
Bioelectric Data Acquisition,” 4th IEEE/EMBS International Summer School and
Medical Devices and Biosensors, Cambridge, Aug. 19-22, 2007, pp. 147-150.
[18] Gil-Cho Ahn, Dong-Young Chang, M. E. Brown, N. Ozaki, H. Youra, K. Yamamura,
K. Hamashita, K. Takasuka, G. C. Temes, Un-Ku Moon, “A 0.6-V 82-dB delta-sigma
audio ADC using switched-RC integrators, ” IEEE J. Solid-State Circuits,” vol. 40,
Dec. 2005, pp. 2398-2407.
[19] A. Gundel, W. N. Carr, “A Micro Power Sigma-Delta A/D Converter in 0.35-μM
CMOS for Low Frequency Applications,” IEEE Long Island Systems, Applications
and Technology Conference, Farmingdale, New York, May 4, 2007, pp. 1-7.
[20] M. Dessouky, A. Kaiser, “Very low-voltage digital-audio ΔΣ modulator with 88-dB
dynamic range using local switch bootstrapping,” IEEE J. Solid-State Circuits, vol.
36, Mar. 2001, pp. 349-355.
[21] M. F. Snoeij, O. Bajdechi, J. H. Huijsing, “A 4th-order switched-capacitor
sigma-delta A/D converter using ahigh-ripple Chebyshev loop filter,” IEEE Int. Symp.
on Circuits and Systems, Sydney, May 6-9, 2001, pp. 615-618.
[22] Chih-Jen Cheng, Shuenn-Yuh Lee, “A low-voltage adaptive switched-current SDM
for bio-acquisition microsystems,” IEEE Int. Symp. on Circuits and Systems, Greece,
May 21-24, 2006, pp. 341-344.
[23] P. G. Drennan, M. L. Kniffin, D. R. Locascio, “Implications of Proximity Effects for
Analog Design,” IEEE Custom Integrated Circuit Conference, San Jose, California,
Sept. 10-13, 2006, pp. 169-176.