WiMAX主要為一種提供高頻寬、長距離傳輸的無線寬頻技術。類比/數位轉換器(A/D Converter)在其系統中扮演極其重要的角色。超取樣和 調變技術則是早已被應用於現代超大型積體電路中的類比數位轉換介面。由於超取樣的特性，使得三角積分調變器通常都被限制在音頻信號應用上。隨著超大積體電路製程的改良，使許多的研究逐漸轉移至寬頻帶的應用上，如GSM、WCDMA、Bluetooth、xDSL及WiMAX等。

    隨著無線通信的進步，系統上需要做到高速高解析度的類比/數位轉換器需要高取樣率及高階數。在考量低電壓及低功率的條件下，低階三角積分調變器已無法滿足這高頻寬需求，所以高階多位元三角積分調變器在這高頻寬系統是必須的。而未來產品發展導向朝向體積小巧、價格低廉、及較長待機時間發展，因此SOC(System-on-Chip)及低功率消耗設計概念將是未來無線寬頻及行動通訊技術發展之不可或缺的兩個重要因素。

    本論文所研究的方向為設計並實現應用於WiMAX寬頻三角積分調變器。為了配合WiMAX系統，電路設計是一個非常大的挑戰。選擇系統架構上，我們選擇超取樣ADC，它擁有適應性、可程式性，以及對類比電路的非理想特性不敏感。而且這項技術還有另外一個優點，它能讓前置的防重疊濾波器規格要求得以減輕。還有它所消耗的功率和雜訊都並不嚴重。在設計考量上，因為類比電路中的積分器會產生許多非理想效應，如有限的直流增益，電容偏差…等等，以及回授路徑上有數位轉類比轉換器(D/A Converter)的非線性效應，這些都會影響我們高階多位元三角積分調變器效能。本論文中，我們將這些非理想效應以Matlab這套軟體來訂定改良出更精準的高階多位元三角積分調變器效能。經由模型來最佳化系統係數及電路規格，以期節省設計的時間。最後利用HSPICE來輔助我們設計模擬出我們所要的電路結果。

    本篇論文所提出之應用於WiMAX之寬頻三角積分調變器，在0.18微米1P6M標準製程中實現，工作電壓為1.8V，系統WiMAX頻寬為10MHz，取樣頻率為160MHz，超取樣比為8，模擬結果為取樣頻率160MHz下，其動態範圍為80dB，而最大的訊號雜訊失真比大約為78dB。

WiMAX is a mainly wireless wideband technique for high bandwidth and long distance. The analog-to-digital (A/D) converters play an important role in the system. The over-sampling and noise shaping techniques are applied in analog to digital conversion interface of modern very-large-scaled integrated circuits. Duo to the over-sampling characteristics, delta sigma (ΔΣ) modulators are limited on the application of voice band signals. As the integrated circuits process is improved, it makes many researches transferring to wide-bandwidth applications gradually, such as GSM, WCDMA, Bluetooth, xDSL, and WiMAX.

   With the progress of wireless communication, A/D converters need higher oversampling ratio and order to achieve the higher speed and resolution in the system, Duo to the requirements of low voltage and low power consumption, the low order delta sigma modulators are not suitable for the high bandwidth system. So, the high order Multibits delta sigma modulator is necessary in the wideband system. The coming products are expected to integrate for less chip area, low cost, and low power consumption. Therefore, the SOC (System on Chip) and low power consumption are the most important concepts in the development for wireless and modern communication systems. 

   In this thesis, we design and impletement Wideband Delta Sigma Modulators for WiMAX. For fitting WiMAX system, the circuit design is a great challenge. Our choice is a delta-sigma ADC, because it has great features for adaptability、programmability, and nonsensitivity to analog components such as the device mismatch and amplifier gain. In addition, it has other advantage of relaxing the requirements of the analog anti-aliasing filters in the AD converters. On the other hand, there is no significant power consumption and noise penalty for the AD conversion of the   modulator. Furthermore, the circuit non-idealities effects also can be included in our architectures to predict the final performance of actual the ΔΣ modulators. According to these non-idealities models and analyses, we can obtain the optimum circuit specifications to implement our ΔΣ modulator.   

   In this thesis, Wideband Delta Sigma Modulators for WiMAX is implemented in a standard 0.18-μm 1P6M CMOS technology. The simulation results show that the bandwidth is 10MHz；the sampling frequency is 160MHz；oversampling ratio is 8；the dynamic range and signal to noise distortion ratio are 80 dB and 78 dB

TABLE OF CONTENTS
	
誌謝	
中文摘要	         I
英文摘要	         III
Table of Contents	V

List of Figures	VII

List of Tables	IX

	
Chapter 1 Introduction 1
	
1-1 Motivation 1
1-2 Applications 3
1-3 Organization 5
	
Chapter 2 Fundamentals of Delta Sigma Modulator 6
	
2-1 Introduction 6
2-2 Quantization Noise 7
2-3 Performance Metric 12
2-4 Oversampling Technique 	14
    2.4.1 Nyquist-rate A/D converters 14
    2.4.2 Advantage of Oversampling Technique 15
2-5 Noise-Shaping ΔΣ Modulator 17
2.5.1 First-Order Noise-Shaping 19
2.5.2 Second-Order Noise-Shaping 20
2.5.3 Higher-Order Noise-Shaping 22
2.5.3.1 Single-Loop Topologies 23
2.5.3.2 Multi-stage Cascoded Delta Sigma Modulator 25
2-6 Multibit Quantization ΔΣ Modulator 27
2-7 Summary 30
	
Chapter 3 System Design 31
	
3-1 Introduction 31
3-2 Top-Down Design 31
3-3 Proposed Architecture 32
3-4 Nonideal Consideration 	36
    3.4.1 Thermal Noise of The Switch 37
    3.4.2 Clock Jitter Noise 39
    3.4.3 Finite Gain Effect of The Operational Amplifier 40
    3.4.4 Finite GBW and SR 42
    3.4.5 Summary 45
	
Chapter 4 Circuit Implementation 48
	
4-1 CMOS Switch 48
4-2 Operational Amplifier 51
4-3 Integrator Circuit 56
4-4 Switch-Capacitor Summing Stage 62
4-5 Four-bit Quantizer 63
4-6 Clock Generator 66
4-7 Data-Weighted Averaging Logic Circuit 67
4-8 Simulation Results 68
4-9 Experimental Consideration 72
4.9.1 Test Setup	72
4.9.2 Layout	72
4-10 Summary 	74
	
Chapter 5 Conclusions and Future work 75
	
5-1 Conclusions 75
5-2 Future work 76
	
Reference 77


LIST OF FIGURES
		
Figure 1.1     Zero-IF receiver architecture for WiMAX 4
	
Figure 2.1 (a) A Model of the quantizer, (b) The linear model, (c) Input-output characteristic of a B-bit quantizer, (d) one-bit quantizer, (e) The quantization error of a B-bit quantizer, and (f)  a one-bit quantizer 8
Figure 2.2     (a) Probability density function (PDF), (b) power spectral density (PSD) of the quantization error, and (c) transfer function of the quantization error to the output 11
Figure 2.3 SNDR/SNR versus signal power of the power of an ADC 14
Figure 2.4 Quantizer and its linear model 16
Figure 2.5 Effect of the oversampling rate conversion 16
Figure 2.6 (a) General structure of a noise-shaping ADC, and (b) its linearized model 18
Figure 2.7  A first-order ΔΣ modulator 20
Figure 2.8  A second-order ΔΣ modulator 21
Figure 2.9  The power spectral density of the first-order and the second-order noise-shaping 22
Figure 2.10 The single-loop L-order delta sigma modulator 24
Figure 2.11 The interpolative ΔΣ modulator 25
Figure 2.12 General structure of a cascaded delta sigma modulator 27
Figure 2.13 A linear model of multi-bit modulator with DAC errors 28
Figure 2.14 Power spectrum of DAC error 29
	
Figure 3.1 Empirical SNDR limit for modulators with 4-bit quantization 32
Figure 3.2 The system block diagram without the NTF zero optimization in this application 33
Figure 3.3 SNDR without the NTF zero optimization in this application 33
Figure 3.4 The proposed DSM architecture 35
Figure 3.5 The poles and zeros of our proposed system 35
Figure 3.6 Output spectrum of ideal modulator 36
Figure 3.7 (a) SC integrator, (b) sampling mode, and (c) evaluating mode 38 
Figure 3.8  NDR versus the variation of Cs 39
Figure 3.9  SNDR versus clock jitter 40
Figure 3.10 Behavior models of (a) ideal integrator, (b) leaky integrator 41
Figure 3.11 SNDR versus DC gain of the opamp 42
Figure 3.12 Evolution of evaluating phase 43
Figure 3.13 SNDR versus GBW of the opamp 44
Figure 3.14 SNDR versus SR of the opamp 44
Figure 3.15 The output spectrum of the modulator with non-idealities by MATLAB 46
Figure 3.16 The dynamic range of the modulator 47
	
Figure 4.1  Transferred curves of the (a) NMOS (b) PMOS (c) TG 49
Figure 4.2  Use of complementary switches to reduce charge injection 50
Figure 4.3  The equivalent Ron of different size of TG 51
Figure 4.4  The schematic of the telescopic amplifiers 54
Figure 4.5  SC CMFB circuit 55
Figure 4.6  Wide swing bias circuit 55
Figure 4.7  (a) First integrator stage (b) second integrator stage (c) third integrator stage (d) fourth integrator stage, and (e) fifth integrator stage 57
Figure 4.8  SC summing stage 63
Figure 4.9  4-bit quantizer 64
Figure 4.10 Differential SC comparator 65
Figure 4.11 Comparator circuit 65
Figure 4.12 Clock generator 66
Figure 4.13 The simulation result of the clock generator 67
Figure 4.14 Block diagram of the DWA logic circuit 68
Figure 4.15 Output spectrum of the modulator 69
Figure 4.16 The dynamic range of the modulator 70
Figure 4.17 Experimental test setup73
Figure 4.18 Layout of the experimental modulator 74

LIST OF TABLES
	
Table 3.1  The specifications of the proposed architecture 45
	
Table 4.1  Function of the equivalent Ron 49
Table 4.2  Ron with different size 51
Table 4.3  Comparison of performance of various opamp topologies 52
Table 4.4  The opamp specification 53
Table 4.5  Performance summary of the telescopic OTA 56
Table 4.6  The coefficients of capacitors 62
Table 4.7  SNDR with process variations 70
Table 4.8  SNDR with supply voltage variations 71
Table 4.9  Performance summary 71
Table 4.10 ΔΣ modulator performance comparison 72

[1]S. R Norsworthy, R. Schreier, and G. C. Temes, “Delta-Sigma Data Converters: Theory Design, and Simulation,”IEEE Press, New York, 1997.

[2]B. J. Farahani, M. Ismail, “Adaptive Sigma Delta ADC for WiMAX Fixed Point Wireless Applications,” IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Vol.1, pp. 692 – 695, Aug. 2005.  
 
[3]B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995.

[4]Y. Geerts, M. Steyaert, and W. Sansen, Design of Multi-Bit Delta-Sigma A/D Converters, Kluwer Academic Publishers, 2002.

[5]S. Rabii and B. A. Wooley, “The Design of Low-voltage, Low-Power Sigma-delta Modulators,” Kluwer Academic Publishers, Boston/Dordrecht/ London, 1999.

[6]K. C.-H. Chou, S. Nadeem, W. L. Lee, and G. C. Sodini, “A higher-order topology for interpolative modulators for oversampling A/D converters,” IEEE Trans. Circuits and Syst. II, vol. 37, pp. 309-318, March 1990.

[7]S. R. Norsworthy, R. Schreier, and G. C. Temes, Eds., Delta-Sigma Data Converters: Theory, Design, and Simulation, New York: IEEE Press, 1996.

[8]P. Kiss, J. Silva, A. Wiesbauer, T. Sun, U. Moon, and G. C. Temes, “Adaptive correction of analog errors in MASH ADCs- Part II. Correction using test-signal inhection,” IEEE Transaction on Circuit and Systems II, vol. 47, no. June. 2000.

[9]“ETS 300 577, BSM: Digital Cellular Telecommunications System (Phase 2); Radio Transmission and Reception (GSM 05.05 Version 4.19.1),” European Telecommunication Standard Institute (ETSI), 1997.

[10]T. Hayashi, Y. Inabe, K. Uchimura, and T. Kimura, “A multistage delta-sigma modulator without double integration loop,” in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, February 1986, vol. 39, pp. 182–183.

[11]Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, and T. Yoshitome, “A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping,” IEEE Journal of Solid-State Circuits, vol. 22, no. 12, pp. 921–929, December 1987.

[12]K. Uchimura, T. Hayashi, T. Kimura, and A. Iwata, “Oversampled A-to-D and DtoA converters with multistage noise shaping modulators,” IEEE Transactions on Accoustics, Speech, and Signal Processing, vol. 36, no. 12, pp. 1899–1905, December 1988.

[13]J. Steensgaard-Madsen, High-Performance Data Converters, Ph.D. thesis, The Technical University of Denmark, Department of Information Technology, March 8, 1999.

[14]A. Wiesbauer and G. C. Temes, “Adaptive digital leakage compensation for MASH delta-sigma ADCs,” Research report, Oregon State University, Department of Electrical and Computer Engineering, July 31, 1997.

[15]J. -B. Shyu, G. C. Temes, and F. Krummenacher, “Arandom error effects in matched  MOS capacitors and current sources,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 948-955, Dec. 1984.

[16]P.-C. Chou, Dual-Mode Sigma-Delta A/D Converter for Wideband Receiver Applications, Ph.D. thesis, Tamkang University of Taiwan, Department of Electrical Engineering, June,2004.

[17]R. E. Radke, A. Eshraghi, and T. S. Fiez, “A 14-bit current-mode sigma-delta DAC  based upon rotated data weighted averaging,” IEEE J. Solid-State Circuits, vol. 35, pp. 1074–1084, Aug. 2000.

[18]T.-H. Kuo, K.-D. Chen, and H.–R. Yeng, “A wideband CMOS sigma-delta modulator  with incremental data weighted averaging,” IEEE J. Solid-State Circuits, vol. 37, no. 1, pp. 11-17, Jan. 2002.

[19]J. G. Kenney and L. R. Carley, “Design of Multibit Noise-Shaping Data Converters,” Analog Integrated Circuits Signal Processing Journal, vol. 3, pp. 259-272, 1993.

[20]B. Razavi, Design of Analog Integrated Circuits, McGRAW-HILL, 2003.

[21]D. A. Johns, K. Martin, Analog Integrated Circuits design, Wiley, 1997.

[22]Y. Greets, M. S. J. Steyaert, and W. Sansen, “A High Performance Multibit Delta-Sigma ADC,” IEEE J. Solid-State Circuits, vol. 35, no 12, pp. 1829-1840, December 2000. 

[23]Y. Greet, M. Marques, M. S. J. Steyaert, and W. Sanaen, “A 3.3-V, 15-bit Delta- Sigma ADC with a Signal Bandwidth of 1.1MHz for ADSL Applications,” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 927-936, July 1999.

[24]J. Yu, and F. Maloberti, “A Low-Power Multi-Bit ΔΣ Modulator in 90-nm Digital  CMOS Without DEM” IEEE J. Solid-State Circuits, vol. 40, no 12, pp. 2428-2436, December 2005. 

[25]Y. Greets, M. S. J. Steyaert, and W. Sanaen, “A High-performance Multibit ΔΣ CMOS ADC” IEEE J. Solid-State Circuits, vol. 35, no 12, pp. 1892-1840, December 2000. 

[26]P. Balmelli, and Q. Huang, “A 25-MS/s 14-b 200-Mw ΔΣ Modulator in 0.18-μm CMOS” IEEE J. Solid-State Circuits, vol. 39, no 12, pp. 2428-2436, December 2004. 

[27]A. Rusu, D. Rodriquez, and M. Ismail, “Reconfigurable ADCs Enable Smart Radios for 4G Wireless Connectivity” IEEE Circuits and devices Magazine, May 2006.