近幾年來，在通訊應用過程中，由於便攜式電子產品可觀的發展，低功率電路發展已經被深入的研究。面對此目標，藉由先進CMOS技術的繼續發展，很多低電壓和低功率設計被此因素所激勵。雖然如此，但隨著供應電壓的減少，此結果阻礙了應用於寬頻之高解析度、高準確性之低功率類比數位轉換器的發展。
此論文提出應用於寬頻之三階低失真、多位元之三角積分調變器。修改過之分佈式前饋串級積分器架構再次被改善，在實現上，調變器在量化器前不需要一個加法器，進而節省電源功率消耗，且在此被改善的調變器中，最佳化了放大器的需求電流，使得縮小了總共電流。在此多位元IMCIFF調變器中。此電路原理已經被實現在三階四位元三角積分調變器，且已經於0.18 μm 製程被製作。操作於頻寬200 kHz，使用時脈頻率為13.76 MHz之調變器，模擬之訊號雜訊脈衝比為93.69 dB。操作於電源供應電壓為1.8 V時，此電路之總消耗功率為4.034 mW。

In recent years, there has been a dramatic proliferation of research concerned with the low-power circuits due to the substantial growth of the portable electronic products in communication applications [1-3]. Toward this aim, many low-voltage and low-power designs have been devoted to with the incitation of the continuing progress of the advanced CMOS technology [4-5]. Nevertheless, the decrease of supply voltage retards the development of the low-power analog-to-digital converters (ADCs) in high-resolution high-accuracy wide-bandwidth applications.
This thesis presents the improved third-order low-distortion multi-bit delta-sigma modulator for wideband applications. The improvement of modified cascade integrators with distributed feedforward (IMCIFF) structure without summer in front of quantizer is realized to save the power consumption in the presented modulator. We take the optimum current of all Opamps in this improved modulator and make the total current be reduced. The prototype circuit is realized in the third-order multi-bit Delta-sigma (ΔΣ) modulator, which has been fabricated in 0.18μm 1P6M CMOS process. The simulated signal-to-noise plus distortion ratio (SNDR) of the modulator within a 200 kHz of bandwidth under a 13.76 MHz of clock rate is 93.69 dB. The total power consumption of the modulator is 4.034 mW at a 1.8 V of supply voltage.

Table of Contents
CHAPTER 1 INTRODUCTION.......................................................................................... 1
1.1 Motivation .................................................................................................................. 1
1.2 Organization ............................................................................................................... 2
CHAPTER 2 FUNDAMENTALS OF ΔΣ MODULATOR.................................................. 3
2.1 Introduction ................................................................................................................ 3
2.2 Performance Calculation ............................................................................................ 4
2.2.1 Resolution and Effective Number of Bits (ENOB) ................................ 4
2.2.2 Signal-to-Noise Ratio (SNR).................................................................. 5
2.2.3 Signal-to-Noise plus Distortion Ratio (SNDR) ...................................... 5
2.2.4 Spurious Free Dynamic Range (SFDR) ................................................. 5
2.2.5 Dynamic Range (DR) ............................................................................. 5
2.3 Quantization ............................................................................................................... 6
2.3.1 Single-bit Quantization........................................................................... 6
2.3.2 Multi-bit Quantization ............................................................................ 8
2.3.2.1 Mid-rise Quantizer............................................................................... 8
2.3.2.2 Mid-tread Quantizer ............................................................................ 9
2.3.2.3 Nonidealities of the Multi-bit Quantizer ........................................... 10
2.3.3 Quantization Error ................................................................................ 10
2.4 Oversampling Technique.......................................................................................... 12
2.5 Noise Shaped ΔΣ Modulator .................................................................................... 14
2.5.1 First-Order Noise Shaping.................................................................... 15
2.5.2 Second-Order Noise Shaping ............................................................... 18
2.5.2.1 Traditional Topology ......................................................................... 18
2.5.2.2 Low Distortion Topology .................................................................. 20
2.5.3 Higher Order Noise Shaping ................................................................ 21
2.5.3.1 Single Loop Topology ....................................................................... 23
2.5.3.2 Cascaded Topology............................................................................ 24
2.6 Multi-bit Quantization .............................................................................................. 25
2.7 Summation Circuit.................................................................................................... 26
2.7.1 Switch Capacitor Summing............................................................... 26
2.7.2 Summation Opamp............................................................................27
2.6.2.3 Charge Sharing .................................................................................. 28
CHAPTER 3 THE DESIGN OF ΔΣ MODULATOR WITH MCIFF STRUCTURE........ 29
3.1 Introduction .............................................................................................................. 29
3.2 Switched-Capacitor Circuits..................................................................................... 29
3.2.1 Paraistic-Insensitive Integrator............................................................. 30
3.2.1.1 Noninverting Delaying Integrator ..................................................... 30
3.2.1.2 Delay-Free Integrator ........................................................................ 32
3.2.2 Three-Input Summing Using Switched-Capacitor Circuits ................ 32
3.3 Architecture of Modified CIFF ΔΣ Modulator......................................................... 33
3.3.1 ΔΣ Modulator with Input-Feedforward Path Structure ........................ 34
3.3.2 Conventional third-order ΔΣ modulator with the CIFF structure......... 34
3.3.3 Third-order ΔΣ Modulator with Modified CIFF structure ................... 35
3.4 Simulation Result with Matlab................................................................................. 37
3.4.1 Behavioral Simulation without Nonideality Model of Opamp ............ 37
3.4.2 Behavioral Simulation with Nonlinearity Model of Opamp ................ 39
3.4.3 Behavioral Simulation with Thermal Noise and RMS Jitter................ 40
3.5 Fully Differential Telescopic Opamp ....................................................................... 41
3.5.1 Common Mode Feedback Circuit (CMFB).......................................... 43
3.5.2 Four-Out Bias Circuit ........................................................................... 43
3.6 Multi-bit Quantizer................................................................................................... 46
3.6.1 R-String Multi-bit Quantizer ................................................................ 46
3.6.2 Two Stage Comparator ......................................................................... 48
3.7 Dynamic Element Matching (DEM) ........................................................................ 49
3.7.1 Data Weighted Averaging (DWA) ........................................................ 49
3.8 Non-Overlapped Clock Generator............................................................................ 50
3.9 Implementation of Third-Order Multi-bit MCIFF Modulator.................................. 51
3.10 Consideration of Measurement................................................................................. 55
3.10.1 Input Termination Circuit ..................................................................... 57
3.10.2 Reference Circuit.................................................................................. 58
3.10.3 LC Filter Tank....................................................................................... 59
3.10.4 Pin Configuration and DUT Board....................................................... 60
3.11 Experimental Results................................................................................................ 61
3.11.1 The Discussion of Experimental Results.............................................. 62
CHAPTER 4 IMPROVED ΔΣ MODULATOR WITH MCIFF STRUCTURE................. 65
4.1 Introduction .............................................................................................................. 65
4.2 How to Get The Minimum Current of All Opamps.................................................. 65
4.3 Simulation Result for Telescopic Opamp in Hspice................................................. 67
4.3.1 Implementation of Improved Third-Order Multi-bit MCIFF Modulator………………………………………………………………………...68
4.3.2 The Comparison of Performance.......................................................... 70
4.4 Experimental Results for improved modulator ........................................................ 71
4.4.1 The Discussion of Experimental Results.............................................. 74
CHAPTER 5 CONCLUSION ............................................................................................ 76
5.1 Conclusion................................................................................................................ 76
5.2 Future Works ............................................................................................................ 77
BIBLIOGRAPHY .................................................................................................................... 78

List of Figures
CHAPTER 2
Figure 2.1 Block diagram of traditional ADC.................................................................... 3
Figure 2.2 Block diagram of oversampling ADC............................................................... 4
Figure 2.3 SNDR / SNR versus input amplitude................................................................ 6
Figure 2.4 Single-bit quantization and the quantization error ............................................ 7
Figure 2.5 The transfer curve of comparator...................................................................... 8
Figure 2.6 Mid-rise quantization and its quantization error ............................................... 9
Figure 2.7 Mid-tread quantization and its quantization erro .............................................. 9
Figure 2.8 The nonlinearities of the practical multi-bit quantizer.................................... 10
Figure 2.9 The PDF of the quantization error .................................................................. 11
Figure 2.10 The converter used the oversampling technique without noise shaping....... 13
Figure 2.11 The PSD of the quantization error after the lowpass filter............................ 13
Figure 2.12 The technology of the conventional ΔΣ modulator....................................... 14
Figure 2.13 The linear model of the conventional ΔΣ modulator .................................... 15
Figure 2.14 A simple first-order 1-bit ΔΣ modulator........................................................ 16
Figure 2.15 Linear model of the traditional second-order ΔΣ modulator ........................ 18
Figure 2.16 The PSD of the first order and the second order noise shaping .................... 20
Figure 2.17 Linear model of the low distortion second-order ΔΣ modulator................... 20
Figure 2.18 SNR prediction with OSR and Lth-order noise shapping............................. 22
Figure 2.19 The interpolative ΔΣ modulator .................................................................... 23
Figure 2.20 The modified interpolative ΔΣ modulator..................................................... 24
Figure 2.21 The simplified cascaded ΔΣ modulator......................................................... 25
Figure 2.22 Switch capacitor summing ............................................................................ 26
Figure 2.23 Summation Opamp ....................................................................................... 27
Figure 2.24 Charge sharing .............................................................................................. 28
CHAPTER 3
Figure 3.1 Noninverting Delaying Integrator................................................................... 30
Figure 3.2 Noninverting Delaying Integrator on the clock phase, φ............................... 31
Figure 3.3 Noninverting Delaying Integrator on the clock phase, φ2 .............................. 31
Figure 3.4 Delay-Free Integrator...................................................................................... 32
Figure 3.5 Three-input switched-capacitor circuit ........................................................... 33
Figure 3.6 Equivalent graph of three-input switched-capacitor ....................................... 33
Figure 3.7ΔΣ modulator with input-feedforward path structure ...................................... 34
Figure 3.8 Conventional third-order ΔΣ modulator with the CIFF structure ................... 35
Figure 3.9 Third-order ΔΣ modulator with the modified CIFF structure......................... 36
Figure 3.10 Behavioral Simulation Model without Nonideality Model of Opamp.......... 37
Figure 3.11 Output swings of all real integrators ............................................................. 38
Figure 3.12 The power spectrum of the behavioral simulation model............................. 38
Figure 3.13 Opamp’ finite gain with different output voltage level ................................. 39
Figure 3.14 The output spectrum of the MCIFF third-order ΔΣ modulator..................... 39
Figure 3.15 Relative plot between sampling capacitor and DR ....................................... 40
Figure 3.16 Behavioral Simulation result with Thermal Noise and RMS Jitter g............ 41
Figure 3.17 The telescopic Opamp used in the integrator................................................ 42
Figure 3.18 Simulation result of telescopic Opamp on worst case .................................. 42
Figure 3.19 Common mode feedback circuit for telescopic Opamp................................ 43
Figure 3.20 4-out bias circuit for the telescopic Opamps................................................. 44
Figure 3.21 Simulation result of VEnable from low to high................................................ 44
Figure 3.22 Simulation result of VEnable from high to low................................................ 45
Figure 3.23 The curve variation of four bias voltages...................................................... 45
Figure 3.24 The curve variation of MOS in Start-Up circuit ........................................... 45
Figure 3.25 16-Levels R-String Multi-bit Quantizer........................................................ 46
Figure 3.26 Summing of fifteen thermal codes in Multi-bit Quantizer............................ 47
Figure 3.27 Corresponding table of Thermometer code to Binary code .......................... 47
Figure 3.28 Two Stage Comparator in Multi-bit Quantizer ............................................. 48
Figure 3.29 DAC feedback............................................................................................... 49
Figure 3.30 The structure of DWA................................................................................... 50
Figure 3.31 Operation principle of DWA......................................................................... 50
Figure 3.32 Non-overlapped clock generator................................................................... 51
Figure 3.33 The presented third-order Multi-bit MCIFF ΔΣ modulator .......................... 52
Figure 3.34 Inputs of integrators ...................................................................................... 52
Figure 3.35 Outputs of integrators.................................................................................... 53
Figure 3.36 Die photo and layout of the presented ΔΣ modulator ................................... 53
Figure 3.37 The output spectrum of the third-order multi-bit MCIFF ΔΣ modulator...... 54
Figure 3.38 The dynamic range of the third-order multi-bit MCIFF ΔΣ modulator ........ 54
Figure 3.39 The environment setup of chip test ............................................................... 56
Figure 3.40 The input differential signal applied by audio precision............................... 56
Figure 3.41 The input termination circuit......................................................................... 57
Figure 3.42 The reference curve for getting the optimum C1 and C2............................... 58
Figure 3.43 The reference circuit with LM317 ................................................................ 58
Figure 3.44 The reference circuit with OP27 ................................................................... 59
Figure 3.45 LC filter tank................................................................................................. 60
Figure 3.46 The DUT PC Board in measurement ............................................................ 60
Figure 3.47 40-pins configuration plan ............................................................................ 61
Figure 3.48 The binary outputs of the presented chip ...................................................... 61
Figure 3.49 The power spectrum of the MCIFF ΔΣ modulator in measurement ............. 62
Figure 3.50 The bounding line1 and line2 in DIP40 chip ................................................ 63
Figure 3.51 The layout plan with ESD circuit.................................................................. 64
CHAPTER 4
Figure 4.1 The work curve of the integrator with TS/2..................................................... 65
Figure 4.2 The simulation result about the optimum current ........................................... 67
Figure 4.3 Simulation result of telescopic Opamp on worst case .................................... 68
Figure 4.4 Die photo and layout of the improved MCIFF ΔΣ modulator ........................ 69
Figure 4.5 The output spectrum of the improved MCIFF ΔΣ modulator......................... 69
Figure 4.6 The dynamic range of the improved MCIFF ΔΣ modulator ........................... 70
Figure 4.7 The DUT PC Board in measurement .............................................................. 71
Figure 4.8 The 40-pins configuration plan ....................................................................... 72
Figure 4.9 The binary outputs of the chip ........................................................................ 72
Figure 4.10 The bias voltages for the Opamps................................................................. 73
Figure 4.11 Power spectrum of the improved MCIFF ΔΣ modulator in measurement.... 73
Figure 4.12 Dynamic Range of the improved MCIFF ΔΣ modulator in measurement.... 74
List of Tables
CHAPTER 3
Table 3.1 The Performance Summary of the Designed Opamps...................................... 42
Table 3.2 The Performance Summary of the third-order multi-bit MCIFF ΔΣ
modulator......................................................................................................................... 55
Table 3.3 The predicted specification in presented modulator ......................................... 62
Table 3.4 Performance summary of measured simulation result in presented modulator 63
CHAPTER 4
Table 4.1 The Performance Summary of the Designed Opamps...................................... 68
Table 4.2 The Performance Summary of the improved MCIFF ΔΣ modulator ............... 70
Table 4.3 FOM for the design comparisons ..................................................................... 71
Table 4.4 The predicted specification in the improved modulator ................................... 74
Table 4.5 Performance summary of measured simulation result in the improved
modulator......................................................................................................................... 74

[1]	A. Gerosa, A. Bevilacqua, A. Neviani, and A. Xotta, “An optimal architecture for a multimode ADC, based on the cascade of a sigma delta  modulator and a flash converter,” Proc. IEEE Symp. on Circuits and Systems, 21-24, May 2006, pp. 585-588.
[2]	T. Christen, T. Burger , and Q. Huang, “A 0.13 um CMOS EDGE/UMTS/WLAN tri-mode delta sigma ADC with -92dB THD,” Dig. of Tech. Papers IEEE Solid-State Circuits, 11-15, Feb 2007, pp. 240 – 599.
[3]	A. Morgado, D. R. Rocio, and J. M. de la Rosa, “Design of a 130-nm CMOS reconfigurable cascade delta sigma modulator for GSM/UMTS/Bluetooth,” Proc. IEEE Symp. on Circuits and Systems, 27-30, May 2007, pp. 725 – 728.
[4]	N. KiYoung, S. M. Lee, D. K. Su, and B. A. Wooley, “A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion,” IEEE J. solid-state Circuits, Sep 2005, pp. 1855-1863.
[5]	C. H. Kuo, S. C. Chen, and K. S. Chang, A 91dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta-sigma modulator,” The 4th IASTED Conf. Circuits and Systems, 2006.
[6]	J. Silva, U. K. Moon, J. Steensgaard, and G. C. Temes, “Wideband Low-Distortion Delta Sigma ADC Topology,” Electron. Lett., vol. 37, Jun. 2001, pp. 737-738.
[7]	W. L. Lee and C. G. Sodini, “A Topology for Higher-Order Interpolative Coders, “ in Proc of IEEE International Symposium on Circuits and Systems, 1987, pp. 459-462.
[8]	K .C . H. Chao, S. Nadeem, W. L. Lee, and C. G. Sodini, “A Higher-Order Topology for Interpolative Modulators for Oversampling A/D Converts,” IEEE Trans. On Circuits and Systems, vol. 37, Mar 1990, pp. 309-318.
[9]	P. Ferguson, Jr., et al., “ An 18b 20kHz Dual Sigma-Delta A/D Convert, “ Int. Solid-State Circuits Conf., Feb 1991. 
[10]	T. Ritoniemi, T. Karema, and H. Tenhunen, “The Design of Stable High Order 1-Bit Sigma-Dalta Modulators,” in Proc. IEEE ISCAS, May 1990, pp. 3267-3270.
[11]	B. DelSignore, D. Kerth, N. Sooch, and E. Swansoon, “A Monolithic 20-dB Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. SC-29, pp. 1311-1317. 
[12]	R. Schreier, and G. C. Temes, “Understanding Delta-Sigma Data Converters,” IEEE Press Wiley Interscience 2005.
[13]	L. R. Carley, “ A Noise-Shapping Coder Topology for 15+bit Converts,” IEEE J. Solid-State Circuits, vl. 24, no. 2, Apr 1989, pp. 267-273.
[14]	R. J. Van de Plassche and D. Goedhart, “A Monolithic 14-bit D/A Convert,” IEEE J. Solid-State Circuits, vol. SC-14, no. 3, Jan 1979, pp. 552-556.
[15]	B. H. Leung, “Architectures for Multi-bit Oversampled A/D Convert Employing Dybamic Element Matching Techviques,” in Proc. IEEE ISCAS, 1991, pp. 1657-1660.
[16]	B. Leung, “Multi-bit Sigma-Delta A/D Converts Incorporating a Novel Class of Dynamic Element Matching Techniques,” IEEE Trans. On Circuits and Systems II, vol. 39, no. 1, Jan 1992, pp. 35-51.
[17]	F. Chen and B. H. Leng, “A High Resolution Nultibit Sigma-Delta Modulator with Individual Level Averaging.” IEEE J. Solid-State Circuits, vol.30, no. 4, April 1995, pp. 453-460.
[18]	R. T. Baird and T. S. Fiez, “Linearity Enhancement of Multi-bitΔΣ A/D and D/A
Converts Using Data Weighted Averaging,” IEEE Trans. On Circuits and Systems II,
vol. 42, Dec. 1995, pp. 753-762.
[19] Louis A and Williams III, “An Audio DAC with 90 dB Linearity Using MOS to
Metal-Metal Charge Transfer,” ISSCC Digest of Technical Papers, 1998, pp. 58-59.
[20] R. Schreier and B. Zang, “Noise-Shaped Multi-bit D/A Convert Employing Unit
Elements,” Electron Letters, 31, (20), 1995, pp. 1712-1713.
[21] K. Nam, et al, “A low-voltage low-power sigma-delta modulator for broadband
analog-to-digital conversion,” IEEE J. Solid-State Circuits, vol. 40, Sept. 2005, pp.
1855-1864.
[22] A. Gharbiya and D. A. Johns, “On the implementation of input-feedforward
delta-sigma modulators,” IEEE Transactions on circuits and systems, 53(6), Jun 2006,
pp. 453-457.
[23] H. Zare-Hoseini, I. Kale, and O. Shaoei, “Modeling of Switched-Capacitor
Delta-Sigma Modulators in SIMULINK,” IEEE Trans. On Instrumentation and
Measurement, vol. 54, no. 4, Aug 2005, pp. 1646-1654.
[24] S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto, and F. Maloberti,
“Modeling sigma-delta modulator non-idealities in SIMULINK(R) ,” in Proc of IEEE
International Symposium on Circuits and Systems on vol. 2. Jun 1999, pp. 384-387.
[25] R. J. Van de Plassche and D. Goedhart, ‘A monolithic 14-bit D/A converter’, IEEE J.
Solid-State Circuits, vol. SC-14, no. 3, Jan. 1979, pp. 552-556.
[26] Keady and C.Lyden, “Tree structure for mismatch noise-shaping multi-bit DAC,”
Electronics Letters, vol. 33, no. 17, 1994, pp. 1431-1432.
[27] R. T. Baird and T. S. Fiez, “Linearity enhancement of multi-bit delta sigma A/D and
D/A converters using data weighted averaging,” IEEE Trans. Circuits Syst. II, vol. 42,
Dec. 1995, pp. 753–762.
[28] H. Leung, “Architectures for multi-bit oversampled A/D converter employing
dynamic element matching techniques,” in Proc. International Symposium on Circuits
and Systems, 1991, pp. 1657-1660.
[29] Rocio del Rio, Jose M. de la Rosa, Belen Perez-Verdu, Manuel Delgado-Restituto,
Rafael Dominguez-Castro, Fernando Medeiro, and Angel Rodriguez-Vazquez,
“ Highly Linear 2.5-V CMOS ΔΣ Modulator for ADSL+,” IEEE Trans. Circuits Syst.
I, vol. 51, Jan. 2004, pp. 47–62.
[30] A. Morgado, R. R. Del, L. R. De, J. M., F. Medeiro,P. V. Belen, F. V. Fernandez and
R. V. Angel, “Reconfiguration of cascade Sigma Delta modulators for multistandard
GSM, Bluetooth , UMTS and WLAN transceivers,” Circuits and Systems. ISCAS.
Proceedings. IEEE International Symposium on 21-24, May. 2006, pp. 1884-1887.