JPEG在過去被廣為使用的靜態影像壓縮系統，因為他在真實影像的壓縮處理上可以達到很高的壓縮比，而且運算複雜度也很低。然而，JPEG在進行低位元率(Low Bit-rate)的壓縮時，將產生令人難以忍受的方塊效應。JPEG2000 [1-5]是ISO/IEC JTC1/SC29/WG1所制定的最新靜態影像壓縮標準。JPEG2000在做低位元率壓縮時能提供比JPEG更平滑的壓縮品質，除此之外，它還加入了其他很多的功能，像是品質與解析度漸進式(Progrssive)的影像傳輸、興趣範圍(Region of Interest, ROI)編碼，同時支援無失真(Loseless)和失真(Lossy)壓縮，並且還有不錯的錯誤回復能力(Error Resilience)。因為JPEG2000有擁這麼豐富的特色，使得它可以使用在各式各樣的應用上，像是網路傳輸、數位相機、監視系統、數位電影院等。然而，也因為JPEG2000提供如此高的壓縮品質和這麼多的功能，所以它演算法的複雜度也遠高於JPEG。
記憶體的使用是JPEG2000晶片設計中最重要的議題。這篇論文提出一個沒有編碼區塊(Code-block, CB)記憶體的JPEG2000 Encoder電路架構。提出的架構藉由將2D-DWT(2D-Discrete Wavelet Transform)與EBCOT(Embedded Block Coding with Optimized Truncation, EBCOT)編碼順序(Scan Order) 一致化，來完全消除CB(Code-block)記憶體。在沒有CB記憶體的情況下，所提出的自適應方塊編碼(Adaptive Embedded Block Coding, AEBC)電路仍能夠跳過所有多餘的不重要位元平面(Insignificant Bit-plane, IBP)來進行編碼。節省它在處理IBP所花費的時間與功率。並以動態RDO(Dynamic Rate Distortion Optimization)來減少失真壓縮(Lossy Compression)時，EBC的運算量。除此之外，提出的架構所使用的Code-block-based DWT可以支援任意Tile大小與任意階層的DWT。整個所提出的JPEG2000 Encoder僅使用2.2KB的內部記憶體與1.5B/Cycs的外部記憶體頻寬，遠低於目前現有的其他架構。

The amount of memory required for code-block is one of the most important issue in JPEG2000 encoder chip implementation. To overcome the drawbacks caused by the large amount of code-block memory in JPEG2000, this paper proposes a new JPEG2000 encoder architecture without code-block memory. Here we try to unify the output scanning order of the 2D-DWT (discrete wavelet transform) and the processing scanning of the EBCOT (embedded block coding with optimized truncation) and further the code-block memory can be completely eliminated. Since the code-block memory has been eliminated, we propose another approach for embedded block coding (EBC), code-block switch adaptive embedded block coding (CS-AEBC) that can skip the insignificant bit-planes (IBP) to reduce the computation time and save power consumption. Besides, a new rate distortion optimization (RDO) approach is proposed to reduce the computation time when the EBC processes lossy compression operation. The DWT used in this work is a code-block-based DWT, and it can process any tile size of picture and any levels of DWT operation. The total memory required for the proposed JPEG2000 is only 2.2KB internal memory, and the bandwidth required for the external memory is 2.1B/cycle. Compared to other JPEG2000 architectures, our new approach has the cost and performance advantage.

目錄
中文摘要	I
英文摘要	II
內文目錄	II
圖表目錄	VI

第一章 緒論	1
1.1	研究背景與動機	1
1.2	 JPEG 2000 系統概述	5
1.2.1	功能特性	6
1.2.2	編解碼流程	7
1.2.3 離散小波轉換	8
1.2.4 EBCOT演算法	9
1.2.5	JPEG2000編碼器的記憶體需求	12
1.3	本文內容	13
第二章 離散小波轉換	14
2.1 JPEG 2000之離散小波轉換演算法	14
2.2 提昇式架構之簡介	18
2.2.2 邊界訊號延伸之處理	24
第三章	EBCOT演算法	26
3.1	CONTEXT MODELING	26
3.1.1	位元平面編碼(Bit-plane Coding)	26
3.1.2	掃瞄順序(Scanning Order)	28
3.1.3	重要狀態變數(significance State Variables)	29
3.1.4次位元平面編碼(Fractional Bit-plane Coding)	30
3.1.5四種編碼運算(coding Operations)	32
3.2	 以CONTEXT為基礎的二元算術編碼	36
3.3字元層級嵌入式方塊編碼演算法	37
3.3.1	WEBC演算法	38
第四章 本文所提出的架構	44
4.1 CB-BASED DWT	46
4.2 ADAPTIVE EBC	51
4.3 PARALLEL RDO	56
4.4 結論	58
第五章 電路實現與比較	59
5.1 實現結果	59
5.1.1 電路實現結果	59
5.2 過去的研究	60
5.3 與其他架構的比較	61
第六章 結論	63
REFERENCE	64

 
圖表目錄
圖1. 1 JPEG與JPEG 2000之壓縮效率比較	2
圖1. 2 JPEG2000 Part 1的編碼/ 解碼流程	7
圖1. 3二維小波分解	9
圖1. 4 EBCOT演算法的兩個主要部份	10
圖1. 5 品質層實例，5個品質層、6個編碼區塊	12
圖1. 6 JPEG2000系統方塊圖(System Block Diagram)	13

圖2. 1 經過高通濾波器及低通濾波器的訊號	15
圖2. 2小波分解樹	16
圖2. 3二維離散小波轉換子頻帶分解	17
圖2. 4 正向提昇式架構	20
圖2. 5 提昇式5/3離散小波轉換演算法	22
圖2. 6 提昇式9/7離散小波轉換演算法	23
圖2. 7 提昇式5/3離散小波轉換之邊界延伸處理圖	25
圖2. 8 提昇式5/3濾波器之週期對稱延伸圖	25

圖3. 1傳統位元平面編碼的說明	28
圖3. 2 EBCOT Scan Order	29
圖3. 3 Coding Pass	31
圖3. 4 ZC運算相關之鄰點	33
圖3. 5 SC運算相關之4鄰點	35
圖3. 6 RLC運算相關點	36
圖3. 7EBC方塊圖(Block Diagram)	37
圖3. 8 WEBC方塊圖(Block Diagram)	38
圖3. 9 Context Modeling Flow Chart	41
圖3. 10 各圖騰(Pattern)的平均BP層數	42
圖3. 11 各CB的BP數累積分布	43

圖4. 1本文所提出的架構	45
圖4. 2 EBCOT Scan Order	47
圖4. 3 Stripe Line Buffer化簡	48
圖4. 4 CB-based DWT Block方塊圖	49
圖4. 5 DWT電路讀取圖像的掃描順序	50
圖4. 6 HDWT中的暫存器架構	51
圖4. 7 CS-AEBC的電路方塊圖	53
圖4. 8 CS-AEBC演算法示意圖	54
圖4. 9 AEBC的Register Bank架構圖	56
圖4. 10 (a) AEBC with Bit-level RDO. (b)AEBC with Word-Level	57

表3. 1 ZC context 對照表	33
表3. 2 H,V contribution for SC operation	34
表3. 3 SC context and XORbit from H,V contribution	35
表3. 4 MR context	35
表3. 5 CM用到的狀態變數	39
表3. 6 資料膨脹率	43

表5. 1  提出的架構各區塊的Gate Counts、使用的內部記憶體大小及外部記憶體頻寬	60
表5. 2與其他的架構做比較	61

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