隨者手提式電子系統及無線通訊技術快速的發展，所以在需求上更要求低功率的消耗技術，以符合盡可能延長電池生命週期的需求。類比/數位轉換器是無線接收端的核心電路，而超取樣和ΔΣ調變技術則是早已被應用於現代超大型積體電路中的類比數位轉換介面。有別於傳統的Niquist 類比/數位轉換器需要高精確的取樣電路，超取樣ΔΣ調變技術對電路上的雜訊敏感度低，這使得它可以實現於較低成本的標準數位製程中，有效的降低成本並進一步結合類比和數位電路以達到系統整合(SOC)的目標。

配合著無線通信的進步，在系統上要做到高速高解析度的類比/數位轉換器需要高取樣頻率。考量低功率低電壓的前提下，這對一般切換電容電路而言是一大限制，因為切換電容電路上中的高阻抗開關會限制訊號的大小和取樣頻率，儘管有些電路技巧如bootstrapping switch 和 switched-opamp可以克服這些問題，但這些電路技巧在設計上更為複雜困難並仍然有受限於取樣頻率的問題。以連續時間電路來設計三角積分調變器，可以避開這些限制達到高速高解析度的目標，並且不會有一般切換電容電路的缺點(Input-signal sampling errors, Settling-time errors)。另一方面，連續時間三角積分調變器的運算放大器所需單位增益頻寬和迴轉率要求的限制遠比離散時間來得更為減少許多。因此連續時間三角積分調變器被廣泛的使用在寬頻低功率的無線通訊系統。

本論文所研究的方向為設計並實現一個寬頻低功率的連續時間三角積分調變器。為了縮短冗長設計電路的時間、複雜的佈局、減少功率消耗和面積，我們有別於高階系統使用一個運算放大器實現一個極點的傳統設計，近而利用主-被動式的濾波器電路來實現類比/數位轉換器，因此我們重新推導一個二階三角積分調變器的系統，使用連續時間電路來設計，脈衝非時變轉換被使用來將離散時間濾波器轉移函式轉換為連續時間濾波器轉移函式。在此電路實現中，第一級濾波器使用被動電阻電容(passive-RC)電路以減小輸入訊號的振幅，然而也減少失真和雜訊的產生，第二級為連續時間積分器使用主動式電阻電容(active-RC)電路來實現，為了使系統電路之頻率響應達到最佳化設計，我們使用一補償電路方法來解決分離系統極、零點的問題，因此將大幅改善系統效能。電路架構用單一回授路徑方式可以容忍製程電阻電容的變異，而多位元nonreturn-to-zero (NRZ)數位類比轉換器做回授以降低對clock jitter的敏感度。

本篇論文提出一個使用單一放大器之低功率連續時間三角積分調變器設計適用於WCDMA之應用，對此論文的應用已被深入的探討及研究，而且將在0.18微米1P6M標準製程中製作成晶片，其模擬結果顯示在工作電壓為1.8V，輸入頻寬為2MHz，超取樣比為32，取樣頻率128MHz下，輸入訊號為648KHz時，訊號雜訊失真比有67.3dB，其動態輸入範圍為68dB，有效解析度11bits，總功率消耗2.3mW。

In the rapidly growing market, portable electronic system such as wireless communication devices or battery-powered medical devices increases the demand for low-power circuit techniques. Reducing the power dissipation in integrated circuits is required to minimize the recharging cycles or to extend the battery lifetime as much as possible. Delta-Sigma modulators are widely used in receivers because of their high-resolution performance and low power consumption. Moreover, the use of continuous-time loop filters provides several advantages over switched capacitor implementations. The gain-bandwidth product (GBW) and slew rate requirements of the amplifiers are much lower comparing to the discrete time counterpart. This results in further power savings. On the other hand, it allows a continuous-time ADC to operate at high frequencies. Consequently, continuous-time delta-sigma modulators are often used in wireless communications, where a high bandwidth with low power consumption is need.

People usually design the ΔΣ modulator with one amplifier per pole to achieve high order noise shaping. However, this approach can lead to a long design process, complex layout, increasing power, and core area. To overcome these drawbacks, several solutions have been proposed. One of these solutions realizes a second-order passive ΔΣ modulator with a two-pole passive filter and one bit quantizer. On the other hand, an active-passive ΔΣ modulator architecture can reduce these influences. 

In this thesis, low-power second-order continuous-time ΔΣ modulator with only one op amp is designed and implemented. The 1st stage of this modulator is made by a passive filter to minimize the signal amplitude, and the 2nd stage is an active integrator to drive the quantizer. Two compensated inverters are added at the output of the 1st stage filter to isolate the 1st stage and the 2nd stage to optimize the frequency response of the proposed circuit. Our circuit architecture use single-loop topologies which are very tolerant of non-idealities such as RC time-constant variation, multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity.

A low power second-order CT ΔΣ modulator has been implemented by combining an active-RC integrator and a passive filter to achieve a second-order noise shaping. We also use a pair of compensated inverters to improve the performance, and this mechanism can increase the performance about 10 dB. The influences of circuit non-idealities, such as integrator leakage, finite GBW, circuit noise, and clock jitter, on the overall ADC are studied and verified by simulations. This continuous-time delta-sigma modulator achieves a 2 MHz signal bandwidth at 128 MHz sampling frequency operation with 68dB of dynamic range and 67.3dB of peak signal-to-noise-distortion ratio (PSNDR). The circuit is implemented by the standard 0.18-μm 1P6M CMOS technology. The core area is 0.23mm2 (0.36mm x 0.64mm) and the power consumption is only 2.3-mW with 1.8-V power supply. It is suitable for WCDMA applications.

Table of Contents

Chapter 1：Introduction …………………………………………………….1

1.1	Motivation ………………….…………………………………………………….....1
1.2	Applications ………………………………………….…………...…………...……..2
1.3	Organization………………………………………….…………...…………...……..4

Chapter 2：Overview of Delta-Sigma Modulator ………….…….………6

2.1	Introduction ……………………………………...…………………………………....6
2.2	Quantization Noise …………….….…………….........................................................6
2.2.1	Quantization Error with Oversampling ………………………………..……...9
2.2.2	Noise Shaping Delta Sigma Modulator …………………………..……...…..11
2.2.3	First-Order Delta Sigma Modulator …………………………..……….…….12
2.2.4	Multi-Bit Delta Sigma Modulator …………………………..……….…...….14
2.3	Equivalence of Discrete-Time to Continuous-Time Modulator …………………….16
2.3.1	The Impulse-Invariant Transform ……………………………………..….…18
2.3.2	NRZ Transformation ……………..………………………………………….20
2.3.3	Exploiting The Equivalence ………………………..………………….…….23
2.4	Summary ………………………………………………………………………….....25

Chapter 3：System Design ……………………………………….…..…….26

3.1	Introduction ……………………………………………………………………….…26
3.2	System Design ……………………………………………………..……………..…27
3.3	Compensation Circuit Design …………….…………………….…………..…..…...34
3.4	Analysis of Non-Ideal Effects ……………………………………………………….37
3.4.1	Integrator Non-Idealities …………………………….………………………37
3.4.1.1  Leaky CT Integrator ………………………….……………………38
3.4.1.2  Finite Gain Bandwidth ……………………….……………………40
3.4.1.3  Finite Slew Rate …………………………..….……………………43
3.4.1.4  Variation of Time-Constant ……………………..…………………44
3.4.2	Temporal Non-Idealities………………………..........………………………46
3.4.2.1  Excess Loop Delay ……………………….………..…………...…47
3.4.2.2  Clock Jitter ……………………….……….………..…………...…48
3.5	Summary ……………………………………...…………………………………...54

Chapter 4：Circuit Design …………………………………………………55

4.1	Modulator Design …………………..……………………………………………….55
4.2	Integrator Design ………………………………………………………………..57
4.3	Quantizer Design ………………………………………………………………...63
4.3.1	Comparator Design ……...………………………………………..…………64
4.3.2	Design of the Clock Generator ……………………………………..………..66
4.4	DAC Design …………………………………………………………………..…..…67
4.4.1	Current Steering DAC Cell Design …….…………………………..………..68
4.4.2	Design for High Accuracy …….……………..……………………..………..69
4.5	Layout ……………………………………………..……………………...……… ...73
4.6	Simulation Result ………………………………………………………………..…70
4.7	Summary ………………………………………………...………………………..…78

Chapter 5：Conclusion and Future Work ………………………………...79

5.1	Conclusion……………………………………………………………...……………79
5.2	Future Work………..…………………………………………………...……………79

Reference ………………...…………………………………………………81
List of Figures
Figure 1.1: Zero-IF receiver architecture for WCDMA ……………………………………3
Figure 1.2: W-CDMA ………………………………………………………………………3
Figure 2.1: Quantizer and its linear model ………………….……………………………...7
Figure 2.2: The power spectral density of the quantization noise ………………………….7
Figure 2.3: Effect of the oversampling rate conversion ……………………………..……..9
Figure 2.4: (a) A general ΔΣ modulator, (b) linear model of the ΔΣ modulator ……..……11
Figure 2.5: A first-order oversampled ΔΣ modulator ……………………………………..13
Figure 2.6: A linear model of multi-bit modulator with DAC errors ……………………..14
Figure 2.7: Power spectrum of DAC error ………………………………………………..16
Figure 2.8: Discrete-time ΔΣ modulator ………………………………………………….17
Figure 2.9: Continuous-time ΔΣ modulator ……………………………..………………..17
Figure 2.10: Mapping between the discrete-time and continuous-time system …………..19
Figure 2.11: NRZ, RZ, and HZ DAC feedback impulse responses ………………………20
Figure 2.12: A continuous-time ΔΣ modulator ……………………………………………21
Figure 3.1: (a) A discrete-time ΔΣ modulator (b) A continuous-time ΔΣ modulator 
(c) Continuous-time loop filter ΔΣ modulator ………………………..……..28
Figure 3.2: Simulation of the output spectrum …………………………………………....28
Figure 3.3: The proposed system of the CT ΔΣ modulator……………………….……….29
Figure 3.4: The output signal of the first and second stage ………….…………..………..29
Figure 3.5: System SNR vs. the ratio of pole and zero in the first stage ……….…………30
Figure 3.6: Realize the circuit of the circuit of a second-order ΔΣ modulator …...…...…..30
Figure 3.7: Small signal analysis ……………...…………………………..………………31
Figure 3.8: (a) R3 vs. R1/ R2 vs. ωz/ωp …...….....................................….............................32
Figure 3.8: (b) R3 vs. C2 vs. ωz/ωp …...……........................................................................32
Figure 3.8: (c) R3 vs. R1/ R2 vs. C3. .………...…………………….......................………..33
Figure 3.9: (c) Add the compensation circuit in the second-order ΔΣ modulator …….…..34
Figure 3.10: Small signal analysis …………….…………………………………………..35
Figure 3.11: Power spectral density compared ……………….…………………………..36
Figure 3.12: Simplified schematic of a fully different integrator with finite-loop gain A0. …………………………………………………………………………..38
Figure 3.13: Influence of finite dc gain on the IBN …………….……….………………..39
Figure 3.14: Influence of finite gain-bandwidth on the IBN of a second-order ΔΣ modulator ……………………….…………………………………………..41
Figure 3.15: Fully different integrator with frequency-dependent loop gain A0(s), excess phase cancellation by Rz, and additional parasitic capacitances …….……...42
Figure 3.16: Simplified schematic of a fully different integrator with variations due to IC manufacturing process in the employed resistors and capacitors. ……….....43
Figure 3.17: Matlab simulate integrator output ……………………...….…………….…..43
Figure 3.18: Impact of time-constant mismatch   on a second-order CT ΔΣ modulator …………………………….…………...……….………………..45
Figure 3.19: DAC feedback impulse response RDAC,NRZ(t,τd) under the influence of excess loop delay τd ………….……………………………..…….………………..46
Figure 3.20: Jitter error source in typical DT and CT ΔΣ modulator (a) DT modulator (b) CT modulator ………….………………………………….………………..48
Figure 3.21: The pulse type of the feedback signal ……………...…...….………………..50
Figure 3.22: Simulate the power spectral density under clock jitter ( ) …......53
Figure 3.23: Simulate SNR for the implemented CT second-order ΔΣ modulator under clock jitter influence ……………………..………..…...….………………..54
Figure 4.1: Simplified circuit diagram of the ΔΣ modulator ………………………...……55
Figure 4.2: The system simulation result of continuous-time ΔΣ modulator ……......……57
Figure 4.3: Simplified amplifier schematic ...……………………………………………..58
Figure 4.4: Simulation of the amplifier (Gain, Phase Margin and GBW) ….....………….60
Figure 4.5: Simulation of the amplifier (TT、SS、SF、FS、FF ) …...…………...…….……60
Figure 4.6: Simulation of the amplifier (output swing) ………………………..…….……60
Figure 4.7: Simulation of the amplifier (nonlinear) ……………………………...….……61
Figure 4.8: Simulation of the amplifier (slew rate) ………………………………….……61
Figure 4.9: Simulation of the amplifier (CMRR) ……………………….……..…….……61
Figure 4.10: 3-bit quantizer ………..……………………………………………………...63
Figure 4.11: Differential SC comparator ……..…………………………………………...64
Figure 4.12 Latch-type Comparator ……………………..………………………………..65
Figure 4.13 The schematic of clock generator circuit …...………………………………..66
Figure 4.14: Simplified feedback DAC topology …………………………………..…… 68
Figure 4.15: Current cell with cascaded transistor ….………………………..…………...69
Figure 4.16: Monte Carlo simulations of the current source ….………….…..…………...71
Figure 4.17: Gaussian Distribution simulation ….………….………………...…………...72
Figure 4.18: Monte Carlo simulations of the current source ….………….…..…………...72
Figure 4.19: Gaussian Distribution simulation ….………….………………...…………...72
Figure 4.20: Layout plan ………………………………………………………………….73
Figure 4.21: Chip Layout ………………………………………………………………....74
Figure 4.22: The circuit pre-simulation result of continuous-time ΔΣ Modulator………...75
Figure 4.23: The circuit pre-simulation result of continuous-time ΔΣ Modulator………...76
Figure 4.24: SNR versus input power …………………………………………………….76
List of Tables

Table 2.1 s-domain equivalences of z-domain loop filter poles…………………………...24
Table 3.1 Comparison of the performance without and with compensation circuit...…….36
Table 4.1 Performance summary of the two-stage amplifier…………………...…………62
Table 4.2: The simulation results of the system in the different five corners…………...62
Table 4.3: The simulation results of the system with the voltage variation of 10%…….62
Table 4.4: The simulation results of the system in the different temperature…………...62
Table 4.5: Technology mismatch parameters……………………………………………...71
Table 4.6: The pre-simulation results of the system in the different five corners………....77
Table 4.7: The pre-simulation results of the system with the voltage variation of 10%......77
Table 4.8: Pro-simulation result summary of the second-order ΔΣ Modulator…………....77
Table 4.9: Performance summary of the ΔΣ Modulators in the 0.18μm……………..…....78

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