算術邏輯單元(ALU)及乘法器為中央處理器（CPU）核心元件，負責所有的運算，是中央處理器主要消耗功率元件之一，降低此二部分功率消耗，可有助於降低中央處理器功率消耗。

    管線式結構是一種最常應用在高速運算的方式。管線式結構之所以可以達到高速運算是因為其允許每一級的運算皆採同時執行。未來，矽製程漸漸的縮小，而晶片的線路漸漸變多變複雜時，在同步系統中有兩個問題會變的越來越嚴重。即時脈網路會帶來大量的功率消耗，和時脈歪斜導致邏輯電路解出錯誤的值。有一種不一樣的電路需要被設計來解決同步系統中的兩個大問題。因此同步系統被轉換成非同步系統。在非同步的系統中，時脈網路被交握式電路給取代，藉以管理管線的運行。

    在本論文中，我們應用 TSMC 0.35 去模擬乘法器之核心元件：使用一種非同步系統的穩健交握式結構。來設計16*16位元非同步管線式系統之布式乘法器(Booth)，為了使其運算速度提升，布斯乘法器(Booth Multiplier)，並以管線式系統的方式來實現這個非同步布式乘法器(Booth)。

Arithmetic logic unit and multiplier for the CPU core component, responsible for all operations, the central processor is one of power consumption components to reduce power consumption of this two parts, can reduce CPU power consumption.

  Pipeline structure is a common way used in high-speed operation. In the synchronous system, there are two problems Clock network will bring a lot of power consumption and clock skew causes Solve the wrong logic value. There is a different circuit needs to be designed to solve the synchronization system The two major problems. Therefore synchronization system is converted into Asynchronous system. In the asynchronous system In the clock network is to replace the handshake circuit in order to manage the operation of the pipeline.

  In this paper, we apply the TSMC 0.35 to simulate the multiplier core components: use of a robust system of non-synchronous handshaking structure. To design 16 * 16-bit asynchronous pipelined multiplier for distributed systems to improve computing speed, Booth multipliers, and pipeline systems approach to achieve this non-synchronous distributed multiplier.

中文摘要………………………………………………………I
英文摘要………………………………………………………II
目錄…………………………………………………………III
圖目…………………………………………………………VI
表目錄………………………………………………………VIII

第一章	序論………………………………………………1
1.1	研究動機…………………………………………1
1.2	本文內容…………………………………………2
第二章	非同步控制介紹…………………………………3
2.1	非同步電路的特性………………………………3
2.2	非同步控制模式的類型…………………………7
2.3	非同步電路的基本架構…………………………10
第三章	已提出之非同步控制電路討論…………………14
3.1	引言………………………………………………14
3.1.1	三種非同步控制電路探討………………………15
3.2	Muller-C元件之非同步控制電路………………15
3.3	LDA控制元件之非同步控制電路………………18
3.4	新型穩健交握元件之非同步控制電路…………19
3.4.1	控制電路動作原理………………………………21
3.4.2	完成信號產生電路………………………………23
第四章	改良之布式乘法器介紹…………………………27
4.1	數種乘法器介紹…………………………………27
4.1.1	反覆式乘法器……………………………………28
4.1.2	陣列式乘法器……………………………………29
4.1.3	樹狀結構乘法器…………………………………31
4.1.3.1	部份乘積…………………………………………32
4.1.3.2	壓縮樹……………………………………………36
第五章	非同步改良之布式乘法器………………………37
5.1	引言………………………………………………37
5.2	非同步改良布式乘法器…………………………37
5.3	模擬結果…………………………………………42
5.4	模擬結果比較……………………………………45
第六章	結論與未來研究…………………………………46
參考文獻……………………………………………………47
 
圖目錄

圖2.1二相交握協定表示圖……………………………………9
圖 2.2四相交握協定表示圖…………………………………10
圖 2.3 Muller C-Element：(a)符號與(b)卡諾圖 ………11
圖 2.4四相交握訊號協定：(a) Push and (b)Pull Channel……12
圖 2.5四相交握訊號協定：(a) Push and (b)Pull Channel……13
圖 3.1 Muller C-Element 符號卡諾圖與電路範例圖……………16
圖 3.2 LDA 控制電路………………………………………………18
圖 3.3新型穩健交握控制元件電路………………………………19
圖 3.4新型穩健交握電路之時序分析……………………………20
圖 3.5新型穩健交握電路之信號轉換圖…………………………22
圖 3.6動態邏輯電路與完成訊號產生器電路圖…………………23
圖 3.7 DCVSL電路時序分析圖……………………………………24
圖 3.8各種完成訊號檢測電路……………………………………25
圖 3.9 4位元完成訊號檢測電路…………………………………26
圖 3.10完成訊號和動態邏輯DCVSL示意圖………………………26
圖 4.1反覆式乘法器之基本架構圖………………………………28
圖 4.2捨棄式陣列式乘法器之架構圖……………………………30
圖 4.3樹狀結構乘法器 ( Tree Structure Multiplier ) 之基本架構圖……31
圖 4.4布式編碼與部份乘積產生單元電路圖……………………34
圖 4.5全加器組成之4-2 Compressor……………………………36
圖 5.1非同步管線式系統…………………………………………38
圖 5.2布式編碼及部份乘積產生電路……………………………39
圖 5.3全加法器的NMOS Tree 表示………………………………41
圖 5.4各級間的運作………………………………………………42
圖 5.5模擬結果……………………………………………………44


表目錄

表 4.1改良式布式編碼……………………………………………33
表 4.2 8bit乘法器………………………………………………35
表 5.1規格比較……………………………………………………45

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